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lvzhengyang
yosys-tests
Commits
668101bf
Unverified
Commit
668101bf
authored
May 24, 2019
by
Miodrag Milanović
Committed by
GitHub
May 24, 2019
Browse files
Options
Browse Files
Download
Plain Diff
Merge pull request #32 from SergeyDegtyar/master
Add checks for certain cell type into 'misc' tests.
parents
94c60f8a
8f683d8f
Show whitespace changes
Inline
Side-by-side
Showing
70 changed files
with
300 additions
and
86 deletions
+300
-86
misc/delete/top.v
+2
-2
misc/run.sh
+172
-0
misc/scripts/add.ys
+2
-1
misc/scripts/add_global_input.ys
+2
-1
misc/scripts/add_inout.ys
+2
-1
misc/scripts/add_input.ys
+2
-1
misc/scripts/add_output.ys
+2
-1
misc/scripts/add_wire.ys
+2
-1
misc/scripts/assertpmux.ys
+2
-1
misc/scripts/assertpmux_always.ys
+2
-1
misc/scripts/assertpmux_noinit.ys
+2
-1
misc/scripts/blackbox.ys
+2
-1
misc/scripts/chformal.ys
+2
-1
misc/scripts/chformal_assert.ys
+2
-1
misc/scripts/chformal_assert2assume.ys
+2
-1
misc/scripts/chformal_assume.ys
+2
-1
misc/scripts/chformal_assume2assert.ys
+2
-1
misc/scripts/chformal_fair.ys
+3
-1
misc/scripts/chformal_fair2live.ys
+2
-1
misc/scripts/chformal_fair2live_assert2assume.ys
+2
-1
misc/scripts/chformal_live.ys
+2
-1
misc/scripts/chformal_live2fair.ys
+2
-1
misc/scripts/chtype_set.ys
+2
-0
misc/scripts/delete.ys
+2
-1
misc/scripts/delete_cell.ys
+2
-1
misc/scripts/delete_input.ys
+3
-1
misc/scripts/delete_mem.ys
+2
-1
misc/scripts/delete_output.ys
+2
-1
misc/scripts/delete_port.ys
+2
-1
misc/scripts/delete_proc.ys
+3
-1
misc/scripts/delete_wire.ys
+3
-1
misc/scripts/insbuf.ys
+1
-0
misc/scripts/insbuf_cell.ys
+1
-0
misc/scripts/mutate_all.ys
+1
-32
misc/scripts/mutate_cnot0.ys
+1
-0
misc/scripts/mutate_cnot1.ys
+1
-0
misc/scripts/mutate_const0.ys
+1
-0
misc/scripts/mutate_const1.ys
+1
-0
misc/scripts/mutate_inv.ys
+1
-0
misc/scripts/pmuxtree.ys
+2
-1
misc/scripts/qwp.ys
+2
-1
misc/scripts/qwp_alpha.ys
+2
-1
misc/scripts/qwp_dump.ys
+2
-1
misc/scripts/qwp_grid.ys
+2
-1
misc/scripts/qwp_ltr.ys
+2
-1
misc/scripts/qwp_v.ys
+2
-1
misc/scripts/rename.ys
+1
-0
misc/scripts/rename_low.ys
+1
-0
misc/scripts/rename_top.ys
+1
-0
misc/scripts/rmports.ys
+2
-1
misc/scripts/scatter.ys
+2
-1
misc/scripts/setattr_mod.ys
+1
-0
misc/scripts/setattr_set.ys
+1
-0
misc/scripts/setattr_set_proc.ys
+1
-0
misc/scripts/setattr_top.ys
+1
-0
misc/scripts/setattr_unset.ys
+1
-0
misc/scripts/splice.ys
+4
-3
misc/scripts/splice_no_outputs.ys
+2
-1
misc/scripts/splice_no_port.ys
+2
-1
misc/scripts/splice_port.ys
+2
-1
misc/scripts/splice_sel_any_bit.ys
+2
-1
misc/scripts/splice_sel_by_cell.ys
+2
-1
misc/scripts/splice_sel_by_wire.ys
+2
-1
misc/scripts/splice_wires.ys
+2
-1
misc/scripts/splitnets.ys
+2
-1
misc/scripts/splitnets_dpf.ys
+2
-1
misc/scripts/splitnets_driver.ys
+2
-1
misc/scripts/splitnets_format.ys
+2
-1
misc/scripts/splitnets_ports.ys
+2
-1
misc/scripts/supercover.ys
+2
-0
No files found.
misc/delete/top.v
View file @
668101bf
...
...
@@ -24,10 +24,10 @@ endmodule
module
middle
(
input
x
,
input
u
x
,
input
y
,
output
o
)
;
assign
o
=
x
+
y
;
assign
o
=
u
x
+
y
;
endmodule
misc/run.sh
View file @
668101bf
...
...
@@ -17,8 +17,180 @@ if [ $? != 0 ] ; then
exit
0
fi
#cases where some object names are/aren't expected in output file (tee -o result.log in the test script)
cell_failed
=
"0"
expected_string
=
""
expected
=
"1"
if
[
"
$2
"
=
"add"
]
;
then
expected_string
=
"wire width 0
\\\w
"
elif
[
"
$2
"
=
"add_global_input"
]
;
then
expected_string
=
"wire width 32000 input 6
\\\g
i"
elif
[
"
$2
"
=
"add_input"
]
;
then
expected_string
=
"wire width 2 input 6
\\\i
"
elif
[
"
$2
"
=
"add_output"
]
;
then
expected_string
=
"wire width 3 output 6
\\\o
"
elif
[
"
$2
"
=
"add_inout"
]
;
then
expected_string
=
"wire width 3 inout 6
\\\3
4"
elif
[
"
$2
"
=
"add_wire"
]
;
then
expected_string
=
"wire
\\\w
"
elif
[
"
$2
"
=
"assertpmux"
]
;
then
expected_string
=
"cell
\$
assert"
elif
[
"
$2
"
=
"assertpmux_always"
]
;
then
expected_string
=
"cell
\$
assert"
elif
[
"
$2
"
=
"assertpmux_noinit"
]
;
then
expected_string
=
"cell
\$
assert"
elif
[
"
$1
"
=
"blackbox"
]
;
then
expected_string
=
"attribute
\\\b
lackbox 1"
elif
[
"
$2
"
=
"chformal"
]
;
then
expected_string
=
"cell
\$
assert"
expected
=
"0"
elif
[
"
$2
"
=
"chformal_assert"
]
;
then
expected_string
=
"cell
\$
assert"
expected
=
"0"
elif
[
"
$2
"
=
"chformal_assert2assume"
]
;
then
expected_string
=
"cell
\$
assert"
expected
=
"0"
elif
[
"
$2
"
=
"chformal_assume"
]
;
then
expected_string
=
"cell
\$
assume"
expected
=
"0"
elif
[
"
$2
"
=
"chformal_assume2assert"
]
;
then
expected_string
=
"cell
\$
assume"
expected
=
"0"
elif
[
"
$2
"
=
"chformal_fair"
]
;
then
expected_string
=
"cell
\$
fair"
expected
=
"0"
elif
[
"
$2
"
=
"chformal_fair2live"
]
;
then
expected_string
=
"cell
\$
fair"
expected
=
"0"
elif
[
"
$2
"
=
"chformal_fair2live_assert2assume"
]
;
then
expected_string
=
"cell
\$
fair"
expected
=
"0"
elif
[
"
$2
"
=
"chformal_live"
]
;
then
expected_string
=
"cell
\$
live"
expected
=
"0"
elif
[
"
$2
"
=
"chformal_live2fair"
]
;
then
expected_string
=
"cell
\$
live"
expected
=
"0"
elif
[
"
$2
"
=
"delete"
]
;
then
expected_string
=
"module
\\\m
iddle"
expected
=
"0"
elif
[
"
$2
"
=
"delete_proc"
]
;
then
expected_string
=
"process
\$
proc
\$
../top.v:13
\$
1"
expected
=
"0"
elif
[
"
$2
"
=
"delete_input"
]
;
then
expected_string
=
"wire input 1
\\\x
"
expected
=
"0"
elif
[
"
$2
"
=
"delete_output"
]
;
then
expected_string
=
"wire output 3
\\\o
"
expected
=
"0"
elif
[
"
$2
"
=
"delete_port"
]
;
then
expected_string
=
"wire output 4
\\\A
"
expected
=
"0"
elif
[
"
$2
"
=
"delete_cell"
]
;
then
expected_string
=
"cell
\$
mux
\$
ternary
\$
../top.v:16
\$
2"
expected
=
"0"
elif
[
"
$2
"
=
"delete_wire"
]
;
then
expected_string
=
"wire
\\\o
"
expected
=
"0"
elif
[
"
$2
"
=
"delete_mem"
]
;
then
expected_string
=
"cell
\$
memrd
\$
memrd
\$\r
am
\$
../top.v:30
\$
7"
expected
=
"0"
elif
[
"
$2
"
=
"edgetypes"
]
;
then
expected_string
=
"
\$
add"
elif
[
"
$1
"
=
"fmcombine"
]
;
then
expected_string
=
"Combining cells "
elif
[
"
$1
"
=
"insbuf"
]
;
then
expected_string
=
"cell
\$
_BUF_
\$
auto
\$
insbuf"
elif
[
"
$1
"
=
"ltp"
]
;
then
expected_string
=
"Longest topological path in"
elif
[
"
$1
"
=
"mutate"
]
;
then
if
[
"
$2
"
=
"mutate_all"
]
||
\
[
"
$2
"
=
"mutate_cnot0"
]
||
\
[
"
$2
"
=
"mutate_cnot1"
]
||
\
[
"
$2
"
=
"mutate_const0"
]
||
\
[
"
$2
"
=
"mutate_const1"
]
||
\
[
"
$2
"
=
"mutate_inv"
]
;
then
expected_string
=
"
\$
auto
\$
mutate"
fi
elif
[
"
$1
"
=
"mutate_mem"
]
;
then
if
[
"
$2
"
=
"mutate_all"
]
;
then
expected_string
=
"
\$
auto
\$
mutate"
fi
elif
[
"
$2
"
=
"pmuxtree"
]
;
then
expected_string
=
"cell
\$
pmux"
expected
=
"0"
elif
[
"
$1
"
=
"qwp"
]
;
then
expected_string
=
"attribute
\\\q
wp_position"
elif
[
"
$2
"
=
"rename"
]
;
then
expected_string
=
"module
\\\m
id_module"
elif
[
"
$2
"
=
"rename_low"
]
;
then
expected_string
=
"module
\\\n
ewlow"
elif
[
"
$2
"
=
"rename_top"
]
;
then
expected_string
=
"module
\\\n
ew_top"
elif
[
"
$2
"
=
"rmports"
]
;
then
expected_string
=
"wire output 5
\\\c
out"
expected
=
"0"
elif
[
"
$2
"
=
"scatter"
]
;
then
expected_string
=
"
\$
auto
\$
scatter"
elif
[
"
$1
"
=
"scc"
]
||
\
[
"
$1
"
=
"scc_hier_feedback"
]
;
then
expected_string
=
"0 SCCs"
elif
[
"
$1
"
=
"scc_feedback"
]
;
then
expected_string
=
"0 SCCs"
expected
=
"0"
elif
[
"
$1
"
=
"setattr"
]
||
\
[
"
$1
"
=
"setattr_mem"
]
;
then
if
[
"
$2
"
=
"setattr"
]
||
\
[
"
$2
"
=
"setattr_top"
]
||
\
[
"
$2
"
=
"setattr_unset"
]
;
then
expected_string
=
"attribute
\\\u
1"
expected
=
"0"
else
expected_string
=
"attribute
\\\u
1"
fi
elif
[
"
$1
"
=
"sim"
]
||
\
[
"
$1
"
=
"sim_mem"
]
;
then
if
[
"
$2
"
!=
"sim_d"
]
;
then
expected_string
=
"Simulating cycle"
fi
elif
[
"
$1
"
=
"splice"
]
;
then
expected_string
=
"
\$
auto
\$
splice"
elif
[
"
$1
"
=
"splitnets"
]
;
then
if
[
"
$2
"
=
"splitnets_dpf"
]
||
\
[
"
$2
"
=
"splitnets_driver"
]
;
then
expected_string
=
"wire width 8
\$
memwr"
else
expected_string
=
"wire width 8
\$
memwr"
expected
=
"0"
fi
elif
[
"
$1
"
=
"stat"
]
;
then
expected_string
=
"middle 1"
elif
[
"
$1
"
=
"supercover"
]
;
then
expected_string
=
"cell
\$
cover
\$
auto
\$
supercover"
fi
if
[
"
$expected_string
"
!=
""
]
;
then
if
grep
"
$expected_string
"
result.log
;
then
if
[
$expected
=
"1"
]
;
then
cell_failed
=
"0"
else
cell_failed
=
"1"
fi
else
if
[
$expected
=
"1"
]
;
then
cell_failed
=
"1"
else
cell_failed
=
"0"
fi
fi
fi
if
grep
'Assert'
result.log
||
grep
'failed in'
result.log
||
grep
'ERROR'
result.log
;
then
echo
FAIL
>
${
1
}
_
${
2
}
.status
elif
[
$cell_failed
=
'1'
]
;
then
echo
FAIL
>
${
1
}
_
${
2
}
.status
else
echo
PASS
>
${
1
}
_
${
2
}
.status
fi
...
...
misc/scripts/add.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log add -wire w 0
add -wire w 0
tee -o result.log dump
misc/scripts/add_global_input.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log add -global_input gi 32000
add -global_input gi 32000
tee -o result.log dump
misc/scripts/add_inout.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log add -inout \34 3
add -inout \34 3
tee -o result.log dump
misc/scripts/add_input.ys
View file @
668101bf
read_verilog ../top.v
add -input i 2
tee -o result.log add -input i 2
add -input i 2
tee -o result.log dump
misc/scripts/add_output.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log add -output o 3
add -output o 3
tee -o result.log dump
misc/scripts/add_wire.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log add -wire w 1
add -wire w 1
tee -o result.log dump
misc/scripts/assertpmux.ys
View file @
668101bf
read_verilog ../top.v
proc
tee -o result.log assertpmux
assertpmux
tee -o result.log dump
misc/scripts/assertpmux_always.ys
View file @
668101bf
read_verilog ../top.v
proc
tee -o result.log assertpmux -always
assertpmux -always
tee -o result.log dump
misc/scripts/assertpmux_noinit.ys
View file @
668101bf
read_verilog ../top.v
proc
tee -o result.log assertpmux -noinit
assertpmux -noinit
tee -o result.log dump
misc/scripts/blackbox.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log blackbox bb
blackbox bb
tee -o result.log dump
misc/scripts/chformal.ys
View file @
668101bf
read_verilog -sv ../top.v
tee -o result.log chformal -remove
chformal -remove
tee -o result.log dump
misc/scripts/chformal_assert.ys
View file @
668101bf
read_verilog -sv ../top.v
tee -o result.log chformal -assert -remove
chformal -assert -remove
tee -o result.log dump
misc/scripts/chformal_assert2assume.ys
View file @
668101bf
read_verilog -sv ../top.v
tee -o result.log chformal -assert2assume
chformal -assert2assume
tee -o result.log dump
misc/scripts/chformal_assume.ys
View file @
668101bf
read_verilog -sv ../top.v
tee -o result.log chformal -assume -remove
chformal -assume -remove
tee -o result.log dump
misc/scripts/chformal_assume2assert.ys
View file @
668101bf
read_verilog -sv ../top.v
tee -o result.log chformal -assume2assert
chformal -assume2assert
tee -o result.log dump
misc/scripts/chformal_fair.ys
View file @
668101bf
read_verilog -sv ../top.v
tee -o result.log chformal -fair -remove
tee -o res dump
chformal -fair -remove
tee -o result.log dump
misc/scripts/chformal_fair2live.ys
View file @
668101bf
read_verilog -sv ../top.v
tee -o result.log chformal -fair2live
chformal -fair2live
tee -o result.log dump
misc/scripts/chformal_fair2live_assert2assume.ys
View file @
668101bf
read_verilog -sv ../top.v
tee -o result.log chformal -fair2live -assert2assume
chformal -fair2live -assert2assume
tee -o result.log dump
misc/scripts/chformal_live.ys
View file @
668101bf
read_verilog -sv ../top.v
tee -o result.log chformal -live -remove
chformal -live -remove
tee -o result.log dump
misc/scripts/chformal_live2fair.ys
View file @
668101bf
read_verilog -sv ../top.v
tee -o result.log chformal -live2fair
chformal -live2fair
tee -o result.log dump
misc/scripts/chtype_set.ys
View file @
668101bf
read_verilog -sv ../top.v
proc
tee -o d.txt dump
tee -o result.log chtype -set $adff $2
tee -o d1.txt dump
misc/scripts/delete.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log delete middle
delete middle
tee -o result.log dump
misc/scripts/delete_cell.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log delete top/$1
delete top/$2
tee -o result.log dump
misc/scripts/delete_input.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log delete -input middle/x
tee -o res.log dump
delete -input top/x
tee -o result.log dump
misc/scripts/delete_mem.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log delete top/$7
delete top/$7
tee -o result.log dump
misc/scripts/delete_output.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log delete -output middle/o
delete -output middle/o
tee -o result.log dump
misc/scripts/delete_port.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log delete -port top/A
delete -port top/A
tee -o result.log dump
misc/scripts/delete_proc.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log delete top/$3
tee -o resul.log dump
delete top/$1
tee -o result.log dump
misc/scripts/delete_wire.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log delete top/o
tee -o resul.log dump
delete top/o
tee -o result.log dump
misc/scripts/insbuf.ys
View file @
668101bf
read_verilog ../top.v
synth
insbuf
tee -o result.log dump
write_verilog synth.v
misc/scripts/insbuf_cell.ys
View file @
668101bf
read_verilog ../top.v
synth
insbuf -buf $_BUF_ A Y
tee -o result.log dump
write_verilog synth.v
misc/scripts/mutate_all.ys
View file @
668101bf
read_verilog ../top.v
mutate -list 512 -o mutate.ys
script mutate.ys
#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
#tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -ctrlbit 1 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port Y -portbit 1 -wire cout -wirebit 0 -src ../top.v:8 -src ../top.v:12
#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port Y -portbit 1 -wire cout -wirebit 0 -src ../top.v:8 -src ../top.v:12
#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port Y -portbit 1 -wire cout -wirebit 0 -src ../top.v:8 -src ../top.v:12
#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port B -portbit 0 -wire x -wirebit 0 -src ../top.v:3 -src ../top.v:12
#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port B -portbit 0 -wire x -wirebit 0 -src ../top.v:3 -src ../top.v:12
#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port B -portbit 0 -wire x -wirebit 0 -src ../top.v:3 -src ../top.v:12
#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port A -portbit 0 -src ../top.v:12
#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -src ../top.v:12
#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -src ../top.v:12
#tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -ctrlbit 1 -src ../top.v:12
#tee -o result.log mutate -mode cnot1 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -ctrlbit 1 -src ../top.v:12
#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port A -portbit 1 -src ../top.v:12
#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port A -portbit 1 -src ../top.v:12
#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port A -portbit 1 -src ../top.v:12
#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$1 -port Y -portbit 0 -src ../top.v:12
#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$1 -port Y -portbit 0 -src ../top.v:12
#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$1 -port Y -portbit 0 -src ../top.v:12
#tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$1 -port Y -portbit 0 -ctrlbit 1 -src ../top.v:12
#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$1 -port Y -portbit 1 -src ../top.v:12
#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$1 -port Y -portbit 1 -src ../top.v:12
#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$1 -port Y -portbit 1 -src ../top.v:12
#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$1 -port B -portbit 0 -wire y -wirebit 0 -src ../top.v:4 -src ../top.v:12
#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$1 -port B -portbit 0 -wire y -wirebit 0 -src ../top.v:4 -src ../top.v:12
#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$1 -port B -portbit 0 -wire y -wirebit 0 -src ../top.v:4 -src ../top.v:12
#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$1 -port A -portbit 0 -wire cin -wirebit 0 -src ../top.v:5 -src ../top.v:12
#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$1 -port A -portbit 0 -wire cin -wirebit 0 -src ../top.v:5 -src ../top.v:12
#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$1 -port A -portbit 0 -wire cin -wirebit 0 -src ../top.v:5 -src ../top.v:12
tee -o result.log dump
misc/scripts/mutate_cnot0.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -ctrlbit 1 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
tee -o result.log dump
misc/scripts/mutate_cnot1.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log mutate -mode cnot1 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -ctrlbit 1 -src top.v:12
tee -o result.log dump
misc/scripts/mutate_const0.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
tee -o result.log dump
misc/scripts/mutate_const1.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
tee -o result.log dump
misc/scripts/mutate_inv.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
tee -o result.log dump
misc/scripts/pmuxtree.ys
View file @
668101bf
read_verilog ../top.v
proc
tee -o result.log pmuxtree
pmuxtree
tee -o result.log dump
misc/scripts/qwp.ys
View file @
668101bf
read_verilog ../top.v
proc
tee -o result.log qwp
qwp
tee -o result.log dump
misc/scripts/qwp_alpha.ys
View file @
668101bf
read_verilog ../top.v
proc
tee -o result.log qwp -alpha
qwp -alpha
tee -o result.log dump
misc/scripts/qwp_dump.ys
View file @
668101bf
read_verilog ../top.v
proc
tee -o result.log qwp -dump out.html
qwp -dump out.html
tee -o result.log dump
misc/scripts/qwp_grid.ys
View file @
668101bf
read_verilog ../top.v
proc
tee -o result.log qwp -grid 4
qwp -grid 4
tee -o result.log dump
misc/scripts/qwp_ltr.ys
View file @
668101bf
read_verilog ../top.v
proc
tee -o result.log qwp -ltr
qwp -ltr
tee -o result.log dump
misc/scripts/qwp_v.ys
View file @
668101bf
read_verilog ../top.v
proc
tee -o result.log qwp -v
qwp -v
tee -o result.log dump
misc/scripts/rename.ys
View file @
668101bf
read_verilog ../top.v
proc
tee -o result.log rename middle mid_module
tee -o result.log dump
misc/scripts/rename_low.ys
View file @
668101bf
read_verilog ../top.v
synth
tee -o result.log rename low newlow
tee -o result.log dump
misc/scripts/rename_top.ys
View file @
668101bf
read_verilog ../top.v
synth -top top
tee -o result.log rename -top new_top
tee -o result.log dump
misc/scripts/rmports.ys
View file @
668101bf
read_verilog ../top.v
proc
tee -o result.log rmports
rmports
tee -o result.log dump
misc/scripts/scatter.ys
View file @
668101bf
read_verilog ../top.v
proc
tee -o result.log scatter
scatter
tee -o result.log dump
misc/scripts/setattr_mod.ys
View file @
668101bf
read_verilog ../top.v
proc
tee -o result.log setattr -mod -set u 1 top
tee -o result.log dump
misc/scripts/setattr_set.ys
View file @
668101bf
read_verilog ../top.v
proc
tee -o result.log setattr -set u 1 top
tee -o result.log dump
misc/scripts/setattr_set_proc.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log setattr -set u 1 top
tee -o result.log dump
misc/scripts/setattr_top.ys
View file @
668101bf
read_verilog ../top.v
proc
tee -o result.log setattr top
tee -o result.log dump
misc/scripts/setattr_unset.ys
View file @
668101bf
...
...
@@ -2,3 +2,4 @@ read_verilog ../top.v
proc
tee -o result.log setattr -set u 1 top
tee -o result.log setattr -unset u top
tee -o result.log dump
misc/scripts/splice.ys
View file @
668101bf
read_verilog ../top.v
tee -o result.log
splice
splice
proc
tee -o result.log
splice
splice
synth
tee -o result.log splice
splice
tee -o result.log dump
misc/scripts/splice_no_outputs.ys
View file @
668101bf
read_verilog ../top.v
synth
tee -o result.log splice -no_outputs
splice -no_outputs
tee -o result.log dump
misc/scripts/splice_no_port.ys
View file @
668101bf
read_verilog ../top.v
synth
tee -o result.log splice -no_port q_b
splice -no_port q_b
tee -o result.log dump
misc/scripts/splice_port.ys
View file @
668101bf
read_verilog ../top.v
synth
tee -o result.log splice -port q_b
splice -port data_a
tee -o result.log dump
misc/scripts/splice_sel_any_bit.ys
View file @
668101bf
read_verilog ../top.v
synth
tee -o result.log splice -sel_any_bit
splice -sel_any_bit
tee -o result.log dump
misc/scripts/splice_sel_by_cell.ys
View file @
668101bf
read_verilog ../top.v
synth
tee -o result.log splice -sel_by_cell
splice -sel_by_cell
tee -o result.log dump
misc/scripts/splice_sel_by_wire.ys
View file @
668101bf
read_verilog ../top.v
synth
tee -o result.log splice -sel_by_wire
splice -sel_by_wire
tee -o result.log dump
misc/scripts/splice_wires.ys
View file @
668101bf
read_verilog ../top.v
synth
tee -o result.log splice -wires
splice -wires
tee -o result.log dump
misc/scripts/splitnets.ys
View file @
668101bf
read_verilog -sv ../top.v
tee -o result.log splitnets
splitnets
tee -o result.log dump
misc/scripts/splitnets_dpf.ys
View file @
668101bf
read_verilog -sv ../top.v
tee -o result.log splitnets -driver -ports -format www
splitnets -driver -ports -format www
tee -o result.log dump
misc/scripts/splitnets_driver.ys
View file @
668101bf
read_verilog -sv ../top.v
tee -o result.log splitnets -driver
splitnets -driver
tee -o result.log dump
misc/scripts/splitnets_format.ys
View file @
668101bf
read_verilog -sv ../top.v
tee -o result.log splitnets -format ()
splitnets -format ()
tee -o result.log dump
misc/scripts/splitnets_ports.ys
View file @
668101bf
read_verilog -sv ../top.v
tee -o result.log splitnets -ports
splitnets -ports
tee -o result.log dump
misc/scripts/supercover.ys
View file @
668101bf
read_verilog ../top.v
proc
tee -o res.log dump
tee -o result.log supercover
tee -o result.log dump
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