Merge pull request #43 from YosysHQ/aiger_naming_fix

Fix test cases according to new naming

Merge pull request #43 from YosysHQ/aiger_naming_fix
Fix test cases according to new naming
61f5ba72 · Miodrag Milanović · GitHub · d5339b41 · ab07a8d5 · 61f5ba72
Unverified Commit 61f5ba72 authored Jun 29, 2019 by Miodrag Milanović Committed by GitHub Jun 29, 2019
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frontends/read_aiger_ff/testbench.v
+4 -4

frontends/read_aiger_latch/testbench.v
+2 -2

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--- a/frontends/read_aiger_ff/testbench.v
+++ b/frontends/read_aiger_ff/testbench.v
@@ -22,10 +22,10 @@ module testbench;

    top uut (
        .clk (clk ),
-        .n1 (n1 ),
-        .n2 (n2 ),
-        .n3 (n3 ),
-        .n3_inv (n3_inv )
+        .__1__ (n1 ),
+        .__2__ (n2 ),
+        .__3__ (n3 ),
+        .__3b__ (n3_inv )
    );

    always @(posedge clk) begin

--- a/frontends/read_aiger_latch/testbench.v
+++ b/frontends/read_aiger_latch/testbench.v
@@ -21,8 +21,8 @@ module testbench;

    top uut (
        .clk (en ),
-        //.n1 (dinA ),
-        .n1_inv (doutB )
+        //.__1__ (dinA ),
+        .__1b__ (doutB )
    );

    always @(posedge en) begin