Fix tests

architecture/synth_intel/synth_intel_arria10gx.ys

-read_verilog ../top.v
-hierarchy -top top
-proc
-#-assert option was skipped because of unproven cells
-#equiv_opt -assert -map +/intel/arria10gx/cells_sim.v synth_intel -family arria10gx # equivalency check
-equiv_opt -map +/intel/arria10gx/cells_sim.v synth_intel -family arria10gx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-stat
-select -assert-count 12  t:$lut
-select -assert-count 1 t:twentynm_lcell_comb
-select -assert-none t:$lut t:twentynm_lcell_comb %% t:* %D

architecture/synth_intel/synth_intel_cyclonev.ys

@@ -2,10 +2,15 @@ read_verilog ../top.v
 hierarchy -top top
 proc
 #-assert option was skipped because of unproven cells
-#equiv_opt -assert -map +/intel/cyclonev/cells_sim.v synth_intel -family cyclonev # equivalency check
-equiv_opt -map +/intel/cyclonev/cells_sim.v synth_intel -family cyclonev # equivalency check
+#equiv_opt -assert -map +/intel/cyclonev/cells_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -map +/intel/cyclonev/cells_sim.v synth_intel_alm -family cyclonev # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 stat
-select -assert-count 13  t:cyclonev_lcell_comb
-select -assert-none t:cyclonev_lcell_comb %% t:* %D
+select -assert-count 1 t:MISTRAL_ALUT2
+select -assert-count 3 t:MISTRAL_ALUT3
+select -assert-count 1 t:MISTRAL_ALUT4
+select -assert-count 3 t:MISTRAL_ALUT5
+select -assert-count 2 t:MISTRAL_ALUT6
+
+select -assert-none t:MISTRAL_ALUT2  t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_tdp_write_first.ys

@@ -17,13 +17,13 @@ stat
 #Vivado synthesizes 1 RAMB18E1.
 select -assert-count 2 t:BUFG
 select -assert-count 136 t:FDRE
-select -assert-count 13 t:LUT1
-select -assert-count 12 t:LUT2
-select -assert-count 44 t:LUT3
-select -assert-count 9 t:LUT4
-select -assert-count 68 t:LUT5
-select -assert-count 165 t:LUT6
-select -assert-count 190 t:MUXF7
-select -assert-count 76 t:MUXF8
+select -assert-count 10 t:LUT1
+select -assert-count 11 t:LUT2
+select -assert-count 52 t:LUT3
+select -assert-count 6 t:LUT4
+select -assert-count 45 t:LUT5
+select -assert-count 183 t:LUT6
+select -assert-count 188 t:MUXF7
+select -assert-count 71 t:MUXF8
 
 select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_dynpreaddmultadd.ys

@@ -18,9 +18,8 @@ stat
 select -assert-count 1 t:BUFG
 select -assert-count 16 t:FDRE
 select -assert-count 1 t:DSP48E1
-select -assert-count 9 t:LUT3
 select -assert-count 9 t:LUT4
 select -assert-count 6 t:CARRY4
 select -assert-count 8 t:INV
 
-select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT4 t:LUT3 t:CARRY4 t:INV %% t:* %D
+select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT4 t:CARRY4 t:INV %% t:* %D

backends/write_btor/write_btor__shifter.pat

-srl 9 10 11
+srl 9 12 13

simple/alu/gates.ys

 read_verilog ../top.v
 synth -top top
 abc -g gates
-select -assert-count 98 t:$_ANDNOT_
-select -assert-count 465 t:$_AND_
+stat
+select -assert-count 64 t:$_ANDNOT_
+select -assert-count 427 t:$_AND_
 select -assert-count 32 t:$_DFF_P_
-select -assert-count 786 t:$_NAND_
-select -assert-count 43 t:$_NOR_
-select -assert-count 3 t:$_NOT_
-select -assert-count 92 t:$_ORNOT_
-select -assert-count 257 t:$_OR_
-select -assert-count 18 t:$_XNOR_
-select -assert-count 26 t:$_XOR_
+select -assert-count 725 t:$_NAND_
+select -assert-count 19 t:$_NOR_
+select -assert-count 8 t:$_NOT_
+select -assert-count 103 t:$_ORNOT_
+select -assert-count 275 t:$_OR_
+select -assert-count 43 t:$_XNOR_
+select -assert-count 32 t:$_XOR_

simple/alu/luts.ys

 read_verilog ../top.v
 synth -top top
 abc -lut 4
+stat
 select -assert-count 32 t:$_DFF_P_
-select -assert-count 688 t:$lut
+select -assert-count 634 t:$lut