more fixes

frontends/read/testbench.v

 module testbench;
     reg [2:0] in;
 
-	wire patt_out = 0;
-	wire patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire patt_out;
+	wire patt_carry_out;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_aiger/testbench.v

 module testbench;
     reg [2:0] in;
 
-	wire patt_out = 0;
-	wire patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire patt_out;
+	wire patt_carry_out;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_blif/testbench.v

@@ -5,8 +5,8 @@ module testbench;
 	reg patt_carry_out = 0;
 	reg patt_out1 = 0;
 	reg patt_carry_out1 = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_blif_eblif/testbench.v

 module testbench;
     reg a;
 
-	wire b = 1'bx;
+	wire b;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_blif_logic/testbench.v

@@ -5,8 +5,8 @@ module testbench;
 	reg patt_carry_out = 0;
 	reg patt_out1 = 0;
 	reg patt_carry_out1 = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_json/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty/testbench.v

 module testbench;
     reg a;
 
-	wire b = 1'bx;
+	wire b;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty_arith/testbench.v

@@ -5,8 +5,8 @@ module testbench;
 	reg patt_carry_out = 0;
 	reg patt_out1 = 0;
 	reg patt_carry_out1 = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty_diff_inv/testbench.v

 module testbench;
     reg a;
 
-	wire b = 1'bx;
+	wire b;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty_ff/testbench.v

@@ -2,7 +2,7 @@ module testbench;
     reg [2:0] in;
 
 	reg patt_out = 0;
-	wire out = 0;
+	wire out;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty_ff_n/testbench.v

@@ -2,7 +2,7 @@ module testbench;
     reg [2:0] in;
 
 	reg patt_out = 0;
-	wire out = 0;
+	wire out;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty_ff_np/testbench.v

@@ -2,7 +2,7 @@ module testbench;
     reg [2:0] in;
 
 	reg patt_out = 0;
-	wire out = 0;
+	wire out;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty_ff_pn/testbench.v

@@ -2,7 +2,7 @@ module testbench;
     reg [2:0] in;
 
 	reg patt_out = 0;
-	wire out = 0;
+	wire out;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty_ff_pp/testbench.v

@@ -2,7 +2,7 @@ module testbench;
     reg [2:0] in;
 
 	reg patt_out = 0;
-	wire out = 0;
+	wire out;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty_latch/testbench.v

@@ -2,7 +2,7 @@ module testbench;
     reg [2:0] in;
 
 	reg patt_out = 0;
-	wire out = 0;
+	wire out;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty_latch_n/testbench.v

@@ -2,7 +2,7 @@ module testbench;
     reg [2:0] in;
 
 	reg patt_out = 0;
-	wire out = 0;
+	wire out;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty_tri/testbench.v

 module testbench;
     reg a;
 	reg En = 1'b1;
-	wire b = 1'bx;
+	wire b;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/verilog_lexer_assert_assume_restrict/testbench.v

 module testbench;
     reg [2:0] in;
 
-	wire patt_out = 0;
-	wire patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire patt_out;
+	wire patt_carry_out;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");