wire init not good for wire in iverilog

backends/write_aiger/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_blif/testbench.v

@@ -5,8 +5,8 @@ module testbench;
 	reg patt_carry_out = 0;
 	reg patt_out1 = 0;
 	reg patt_carry_out1 = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_btor/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_btor_div_mod/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_btor_logic/testbench.v

@@ -5,8 +5,8 @@ module testbench;
 	reg patt_carry_out = 0;
 	reg patt_out1 = 0;
 	reg patt_carry_out1 = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_btor_shift/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_edif/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_firrtl_logic/testbench.v

@@ -5,8 +5,8 @@ module testbench;
 	reg patt_carry_out = 0;
 	reg patt_out1 = 0;
 	reg patt_carry_out1 = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_firrtl_reduce/testbench.v

@@ -5,8 +5,8 @@ module testbench;
 	reg patt_carry_out = 0;
 	reg patt_out1 = 0;
 	reg patt_carry_out1 = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_firrtl_shift/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_intersynth/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_json/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_smt2_init_assert/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_smt2_reduce/testbench.v

@@ -5,8 +5,8 @@ module testbench;
 	reg patt_carry_out = 0;
 	reg patt_out1 = 0;
 	reg patt_carry_out1 = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_smv_init_assert/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_smv_reduce/testbench.v

@@ -5,8 +5,8 @@ module testbench;
 	reg patt_carry_out = 0;
 	reg patt_out1 = 0;
 	reg patt_carry_out1 = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_smv_shift/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_verilog_concat/testbench.v

 module testbench;
     reg [4:0] in;
 
-	wire [1:0] Ap = 0;
-	wire [2:0] Bp = 0;
-	wire [2:0] Cp = 0;
-	wire [1:0] A = 0;
-	wire [2:0] B = 0;
-	wire [2:0] C = 0;
+	wire [1:0] Ap;
+	wire [2:0] Bp;
+	wire [2:0] Cp;
+	wire [1:0] A;
+	wire [2:0] B;
+	wire [2:0] C;
 
     initial begin
         // $dumpfile("testbench.vcd");