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lvzhengyang
yosys-tests
Commits
5444eb20
Commit
5444eb20
authored
Jul 17, 2019
by
SergeyDegtyar
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Add new test to 'equiv'
parent
0343b35f
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2 changed files
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17 additions
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1 deletions
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-1
equiv/Makefile
+1
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equiv/scripts/equiv_opt_undef.ys
+16
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equiv/Makefile
View file @
5444eb20
...
@@ -59,7 +59,7 @@ $(eval $(call template,equiv_add,equiv_add equiv_add_try ))
...
@@ -59,7 +59,7 @@ $(eval $(call template,equiv_add,equiv_add equiv_add_try ))
$(eval
$(call
template,equiv_add_error,equiv_add_module_context
))
$(eval
$(call
template,equiv_add_error,equiv_add_module_context
))
#equiv_opt
#equiv_opt
$(eval
$(call
template,equiv_opt,equiv_opt
equiv_opt_run
equiv_opt_map))
$(eval
$(call
template,equiv_opt,equiv_opt
equiv_opt_run
equiv_opt_map
equiv_opt_undef
))
$(eval
$(call
template,equiv_opt_error,equiv_opt_unknown_option
equiv_opt_no_opt
equiv_opt_fully_selected_des))
$(eval
$(call
template,equiv_opt_error,equiv_opt_unknown_option
equiv_opt_no_opt
equiv_opt_fully_selected_des))
.PHONY
:
all clean
.PHONY
:
all clean
equiv/scripts/equiv_opt_undef.ys
0 → 100644
View file @
5444eb20
read_verilog ../top.v
prep -flatten -top top
splitnets -ports;;
design -stash gold
read_verilog ../synth_top.v
read_verilog ../logic.v
prep -flatten -top top
splitnets -ports;;
design -stash gate
design -copy-from gold -as gold top
design -copy-from gate -as gate top
equiv_make gold gate equiv
equiv_opt -undef equiv_purge
design -reset
read_verilog ../top.v
write_verilog synth.v
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