Convert test1 to run-test.sh with autotb

architecture/synth_xilinx_srl/generate.py

+#!/usr/bin/python3
+
+# Test 1: pos_clk_no_enable_no_init_not_inferred
+for i in range(131):
+    with open('test1_%d.v' % i, 'w') as fp:
+        fp.write('''
+module test1_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input [31:0] s, output [width-1:0] q);
+generate 
+    wire [depth:0] int [width-1:0];
+    genvar w, d;
+    for (w = 0; w < width; w=w+1) begin
+        assign int[w][0] = i[w];
+        for (d = 0; d < depth; d=d+1) begin
+            \$_DFFE_PP_ r(.C(clk), .D(int[w][d]), .E(1'b0), .Q(int[w][w+1]));
+        end
+        assign q[w] = int[w][depth];
+    end
+endgenerate
+endmodule
+'''.format(i+1))

architecture/synth_xilinx_srl/run-test.sh

+#!/bin/bash
+
+OPTIND=1
+seed=""    # default to no seed specified
+while getopts "S:" opt
+do
+    case "$opt" in
+	S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
+	   seed="SEED=$arg" ;;
+    esac
+done
+shift "$((OPTIND-1))"
+
+# check for Icarus Verilog
+if ! which iverilog > /dev/null ; then
+  echo "$0: Error: Icarus Verilog 'iverilog' not found."
+  exit 1
+fi
+
+#wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/lfsr/generate.py -O generate_lfsr.py -o /dev/null
+#python3 generate_lfsr.py
+python3 generate.py
+${MAKE:-make} -f ../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="-f 'verilog -noblackbox -icells' -p 'synth_xilinx' -l ../../../../techlibs/xilinx/cells_sim.v"

architecture/synth_xilinx_srl/testbench.v

-`include "defines.vh"
-
-module testbench;
-    reg clk;
-
-    initial begin
-        // $dumpfile("testbench.vcd");
-        // $dumpvars(0, testbench);
-
-        #5 clk = 0;
-        repeat (`N*3) begin
-            #5 clk = 1;
-            #5 clk = 0;
-        end
-
-        $display("OKAY");
-    end
-
-    reg [`N-1:0] a;
-    reg e, r;
-    reg [31:0] l;
-    wire [`N-1:0] y;
-    wire [`N-1:0] z;
-
-    top rtl (
-        .clk (clk ),
-        .a (a),
-        .e (e),
-        .r (r),
-        .l (l),
-        .z (y)
-    );
-
-    synth uut (
-        .clk (clk ),
-        .a (a),
-        .e (e),
-        .r (r),
-        .l (l),
-        .z (z)
-    );
-
-    always @(negedge clk) begin
-        e <= $random;
-        r <= $random;
-        l <= $random;
-    end
-
-    generate
-        genvar i;
-        for (i = 0; i < `N; i=i+1) begin
-            always @(posedge clk)
-                a[i] <= $random;
-            assert_dff zp_test(.clk(clk), .test(z[i]), .pat(y[i]));
-            assert_dff zn_test(.clk(~clk), .test(z[i]), .pat(y[i]));
-        end
-    endgenerate
-
-endmodule

architecture/synth_xilinx_srl/ug901.v

-// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug901-vivado-synthesis.pdf
-
-// 8-bit Shift Register
-// Rising edge clock
-// Active high clock enable
-// Concatenation-based template
-// File: shift_registers_0.v
-module shift_registers_0 (clk, clken, SI, SO);
-parameter WIDTH = 32;
-input clk, clken, SI;
-output SO;
-reg [WIDTH-1:0] shreg;
-always @(posedge clk)
-begin
-	if (clken)
-		shreg <= {shreg[WIDTH-2:0], SI};
-end
-assign SO = shreg[WIDTH-1];
-endmodule
-
-// 32-bit Shift Register
-// Rising edge clock
-// Active high clock enable
-// For-loop based template
-// File: shift_registers_1.v
-module shift_registers_1 (clk, clken, SI, SO);
-parameter WIDTH = 32;
-input clk, clken, SI;
-output SO;
-reg [WIDTH-1:0] shreg;
-integer i;
-always @(posedge clk)
-begin
-    if (clken)
-    begin
-        for (i = 0; i < WIDTH-1; i = i+1)
-            shreg[i+1] <= shreg[i];
-        shreg[0] <= SI;
-    end
-end
-assign SO = shreg[WIDTH-1];
-endmodule
-
-// 32-bit dynamic shift register.
-// Download:
-// File: dynamic_shift_registers_1.v
-module dynamic_shift_register_1 (CLK, CE, SEL, SI, DO);
-parameter SELWIDTH = 5;
-input CLK, CE, SI;
-input [SELWIDTH-1:0] SEL;
-output DO;
-localparam DATAWIDTH = 2**SELWIDTH;
-reg [DATAWIDTH-1:0] data;
-assign DO = data[SEL];
-always @(posedge CLK)
- begin
- if (CE == 1'b1)
- data <= {data[DATAWIDTH-2:0], SI};
- end
-endmodule

architecture/synth_xilinx_srl/ug901a.v

+// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug901-vivado-synthesis.pdf
+
+// 8-bit Shift Register
+// Rising edge clock
+// Active high clock enable
+// Concatenation-based template
+// File: shift_registers_0.v
+module shift_registers_0 (clk, clken, SI, SO);
+parameter WIDTH = 32;
+input clk, clken, SI;
+output SO;
+reg [WIDTH-1:0] shreg;
+always @(posedge clk)
+begin
+	if (clken)
+		shreg <= {shreg[WIDTH-2:0], SI};
+end
+assign SO = shreg[WIDTH-1];
+endmodule