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yosys-tests
Unverified Commit 472fed36 by Miodrag Milanović Committed by GitHub
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Merge pull request #13 from SergeyDegtyar/master 

Add tests for issues from 111 to 527 that I could automate.
parents f76690a5 634611c8
Showing with 5221 additions and 44 deletions
regression/Makefile
......@@ -6,7 +6,7 @@ clean::
define template
$(foreach design,$(1),
$(foreach script,verify falsify $(2),
$(foreach script,$(2),
work:: $(design)/work_$(script)/.stamp
$(design)/work_$(script)/.stamp:
......@@ -17,8 +17,8 @@ clean::
))
endef
#case_stmt_assertion
$(eval $(call template,case_stmt_assertion,case_stmt_assertion))
#issue_00790
$(eval $(call template,issue_00790,issue_00790))
#issue_00018
$(eval $(call template,issue_00018,issue_00018))
......@@ -38,7 +38,7 @@ $(eval $(call template,issue_00067,issue_00067))
#issue_00071
$(eval $(call template,issue_00071,issue_00071))
#issue_00078 What should be in top.v?
#issue_00078
$(eval $(call template,issue_00078,issue_00078))
#issue_00081
......@@ -73,34 +73,19 @@ $(eval $(call template,issue_00086,issue_00086))
$(eval $(call template,issue_00088,issue_00088))
#issue_00089
#1. Executing Verilog-2005 frontend.
#Parsing Verilog input from `top.v' to AST representation.
#top.v:6: ERROR: syntax error, unexpected $undefined
#$(eval $(call template,issue_00089,issue_00089))
$(eval $(call template,issue_00089,issue_00089))
#issue_00091
$(eval $(call template,issue_00091,issue_00091))
#issue_00093
# correct behavior
#../top.v:1: syntax error
#../top.v:1: error: syntax error in left side of continuous assignment.
#$(eval $(call template,issue_00093,issue_00093))
$(eval $(call template,issue_00093,issue_00093))
#issue_00095
#../top.v:1: syntax error
#../top.v:1: error: Invalid variable list in port declaration.
#../top.v:1: error: duplicate declaration for net or variable 'c' in 'a'.
#$(eval $(call template,issue_00095,issue_00095))
$(eval $(call template,issue_00095,issue_00095))
#issue_00096
#../top.v:2: syntax error
#../top.v:1: error: syntax error in integer variable list.
#../top.v:2: syntax error
#../top.v:2: error: syntax error in left side of continuous assignment.
#../top.v:2: syntax error
#../top.v:2: error: syntax error in left side of continuous assignment.
#$(eval $(call template,issue_00096,issue_00096))
$(eval $(call template,issue_00096,issue_00096))
#issue_00098
$(eval $(call template,issue_00098,issue_00098))
......@@ -114,5 +99,140 @@ $(eval $(call template,issue_00102,issue_00102))
#issue_00111
$(eval $(call template,issue_00111,issue_00111))
#issue_00114
$(eval $(call template,issue_00114,issue_00114))
#issue_00126
$(eval $(call template,issue_00126,issue_00126))
#issue_00128
$(eval $(call template,issue_00128,issue_00128))
#issue_00132
$(eval $(call template,issue_00132,issue_00132))
#issue_00133
$(eval $(call template,issue_00133,issue_00133))
#issue_00134
$(eval $(call template,issue_00134,issue_00134))
#issue_00160
$(eval $(call template,issue_00160,issue_00160))
#issue_00171
$(eval $(call template,issue_00171,issue_00171))
#issue_00173
$(eval $(call template,issue_00173,issue_00173))
#issue_00174
$(eval $(call template,issue_00174,issue_00174))
#issue_00175
$(eval $(call template,issue_00175,issue_00175))
#issue_00182
$(eval $(call template,issue_00182,issue_00182))
#issue_00183
$(eval $(call template,issue_00183,issue_00183))
#issue_00186
$(eval $(call template,issue_00186,issue_00186))
#issue_00194
$(eval $(call template,issue_00194,issue_00194))
#issue_00195
$(eval $(call template,issue_00195,issue_00195))
#issue_00196
$(eval $(call template,issue_00196,issue_00196))
#issue_00210
$(eval $(call template,issue_00210,issue_00210))
#issue_00253
$(eval $(call template,issue_00253,issue_00253))
#issue_00282
$(eval $(call template,issue_00282,issue_00282))
#issue_00283
$(eval $(call template,issue_00283,issue_00283))
#issue_00287
$(eval $(call template,issue_00287,issue_00287))
#issue_00289
$(eval $(call template,issue_00289,issue_00289))
#issue_00291
$(eval $(call template,issue_00291,issue_00291))
#issue_00300
$(eval $(call template,issue_00300,issue_00300))
#issue_00306
$(eval $(call template,issue_00306,issue_00306))
#issue_00314
$(eval $(call template,issue_00314,issue_00314))
#issue_00317
$(eval $(call template,issue_00317,issue_00317))
#issue_00341
$(eval $(call template,issue_00341,issue_00341))
#issue_00342
$(eval $(call template,issue_00342,issue_00342))
#issue_00349
$(eval $(call template,issue_00349,issue_00349))
#issue_00350
$(eval $(call template,issue_00350,issue_00350))
#issue_00361
$(eval $(call template,issue_00361,issue_00361))
#issue_00362
$(eval $(call template,issue_00362,issue_00362))
#issue_00372
$(eval $(call template,issue_00372,issue_00372))
#issue_00391
$(eval $(call template,issue_00391,issue_00391))
#issue_00432
$(eval $(call template,issue_00432,issue_00432))
#issue_00444
$(eval $(call template,issue_00444,issue_00444))
#issue_00449
$(eval $(call template,issue_00449,issue_00449))
#issue_00457
$(eval $(call template,issue_00457,issue_00457))
#issue_00474
$(eval $(call template,issue_00474,issue_00474))
#issue_00481
$(eval $(call template,issue_00481,issue_00481))
#issue_00502
$(eval $(call template,issue_00502,issue_00502))
#issue_00524
$(eval $(call template,issue_00524,issue_00524))
#issue_00527
$(eval $(call template,issue_00527,issue_00527))
.PHONY: all clean
regression/common.v
module assert_dff(input clk, input test, input pat);
always @(posedge clk)
begin
#2
if (test != pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time);
......@@ -33,6 +34,18 @@ module assert_Z(input clk, input A);
end
endmodule
module assert_X(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A === 1'bX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
module assert_comb(input A, input B);
always @(*)
begin
......
regression/issue_00111/testbench.v
......@@ -21,13 +21,13 @@ module testbench;
begin
state = state + 2300;
key = key + 2500;
end
end*/
top uut (
.state (state ),
.key (key ),
.out (out )
);*/
);
/*genvar index;
generate
......
regression/issue_00114/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.clock (clk )
);
endmodule
regression/issue_00114/top.v 0 → 100644
module top(
input wire clock
);
localparam COUNT = 1600;
reg buffer[0:COUNT-1];
always @(posedge clock) begin : GENERATE
integer ii;
for(ii = 0; ii < COUNT; ii = ii + 1) begin
buffer[ii] <= 1'b0;
end
end
endmodule
regression/issue_00126/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] in = 0;
always @(posedge clk)
in = in + 1;
top uut (
.in_a(in),
.out_vt(out)
);
endmodule
regression/issue_00126/top.v 0 → 100644
module top (in_a, out_vt);
input [1:0] in_a;
output out_vt;
reg [2:0] result;
assign out_vt = result;
always @(*)
begin
result = 3'b000;
case (in_a)
2'b00 : begin
result = 3'b101;
end
2'b01: begin
result = 3'b001;
end
default;
endcase
end
endmodule
regression/issue_00128/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00128/top.v 0 → 100644
module top(b);
input b;
initial $display("%m");
endmodule
regression/issue_00132/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] y;
always @(posedge clk)
begin
a = a + 3;
end
top uut (
.a (a ),
.y (y )
);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
assert_Z check_output(clk,y[index]);
end
endgenerate
endmodule
regression/issue_00132/top.v 0 → 100644
module submod(input [7:0] a, output [7:0] y);
parameter integer increment = 0;
initial begin
if (increment == 0) begin
$display("increment parameter must have a non-zero value!");
//$stop;
end
end
assign y = a + increment;
endmodule
module top(input [7:0] a, output [7:0] y);
parameter integer incr = 0;
submod #(incr) submod_instance (a, y);
endmodule
regression/issue_00133/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] y;
always @(posedge clk)
begin
a = a + 3;
end
top uut (
.a (a ),
.y (y )
);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
assert_Z check_output(clk,y[index]);
end
endgenerate
endmodule
regression/issue_00133/top.v 0 → 100644
module top(input [7:0] a, output reg [7:0] y);
always @* begin:myblock
reg [7:0] myarray [0:1];
myarray[0] = a + 23;
myarray[1] = myarray[0] - 42;
y = myarray[1] + 19;
end
endmodule
regression/issue_00134/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] a = 0;
wire [15:0] y;
always @(posedge clk)
begin
a = a + 3;
end
top uut (
.in_data (a ),
.do (y )
);
genvar index;
generate
for (index=0; index <= 15; index=index+1)
begin: gen_code_label
assert_X check_output(clk,y[index]);
end
endgenerate
endmodule
regression/issue_00134/top.v 0 → 100644
module top ( in_data, do );
input [15:0] in_data;
output [15:0] do;
wire [15:0] out_data;
assign do = out_data;
always @ (*)
begin
Test_task(in_data, out_data);
// out_data = in_data; // This works but above task doesn't
end
task Test_task;
input [15:0] in_d;
output [15:0] out_data;
begin
out_data = in_d;
end
endtask
endmodule
regression/issue_00160/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a = 0;
reg ce = 1;
wire d;
always @(posedge clk)
begin
a = a + 1;
end
top uut (
.CLKIN(clk),
.A (a ),
.CE (ce),
.D1 (d)
);
assert_X check_output(clk,d);
endmodule
regression/issue_00160/top.v 0 → 100644
module Add2 (input [1:0] I0, input [1:0] I1, output [1:0] O);
wire inst0_O;
wire inst1_CO;
wire inst2_O;
wire inst3_CO;
SB_LUT4 #(.LUT_INIT(16'hC33C)) inst0 (.I0(1'b0), .I1(I0[0]), .I2(I1[0]), .I3(1'b0), .O(inst0_O));
SB_CARRY inst1 (.I0(I0[0]), .I1(I1[0]), .CI(1'b0), .CO(inst1_CO));
SB_LUT4 #(.LUT_INIT(16'hC33C)) inst2 (.I0(1'b0), .I1(I0[1]), .I2(I1[1]), .I3(inst1_CO), .O(inst2_O));
SB_CARRY inst3 (.I0(I0[1]), .I1(I1[1]), .CI(inst1_CO), .CO(inst3_CO));
assign O = {inst2_O,inst0_O};
endmodule
module Register2CE (input [1:0] I, output [1:0] O, input CLK, input CE);
wire inst0_Q;
wire inst1_Q;
//SB_DFFE #(.INIT(1'b0)) inst0 (.C(CLK), .E(CE), .D(I[0]), .Q(inst0_Q));
//SB_DFFE #(.INIT(1'b0)) inst1 (.C(CLK), .E(CE), .D(I[1]), .Q(inst1_Q));
SB_DFFE inst0 (.C(CLK), .E(CE), .D(I[0]), .Q(inst0_Q));
SB_DFFE inst1 (.C(CLK), .E(CE), .D(I[1]), .Q(inst1_Q));
assign O = {inst1_Q,inst0_Q};
endmodule
module top (input CLKIN, input A, input CE, output D1);
wire [1:0] inst0_O;
wire [1:0] inst1_O;
Add2 inst0 (.I0(inst1_O), .I1({1'b0,1'b1}), .O(inst0_O));
Register2CE inst1 (.I(inst0_O), .O(inst1_O), .CLK(CLKIN), .CE(CE));
assign D1 = inst1_O[1];
endmodule
regression/issue_00171/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg rst = 1;
reg ce = 1;
wire [3:0] count;
reg [3:0] count_p;
always @(posedge clk)
begin
rst = 0;
end
always @(posedge clk)
if (rst)
count_p <= 4'd0;
else if (ce)
count_p <= count_p + 4'd1;
top uut (
.clk(clk),
.rst (rst ),
.en (ce),
.count (count)
);
genvar index;
generate
for (index=0; index <= 3; index=index+1)
begin: gen_code_label
assert_dff check_output(clk,count[index],count_p[index]);
end
endgenerate
endmodule
regression/issue_00171/top.v 0 → 100644
module top (clk, rst, en, count);
input clk, rst, en;
output reg [3:0] count;
always @(posedge clk)
if (rst)
count <= 4'd0;
else if (en)
count <= count + 4'd1;
endmodule
regression/issue_00173/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [2:0] o;
reg [2:0] i;
always @(posedge clk)
i <= i + 1;
top uut (i[0],i[1],i[2],o[0],o[1],o[2]);
genvar index;
generate
for (index=0; index <= 2; index=index+1)
begin: gen_code_label
assert_dff check_output(clk,o[index],i[index]);
end
endgenerate
endmodule
regression/issue_00173/top.v 0 → 100644
module top
(
input ai, bi, ci,
output reg ao, bo, co
);
always@*
begin
ao=ai;
bo=bi;
co=ci;
{co,co,bo,ao} = {ai,bi,ai,ci}; // Error: multiple assignment to 'co' with blocking assignment
end
endmodule
regression/issue_00174/abc.rc 0 → 100644
# global parameters
set check # checks intermediate networks
#set checkfio # prints warnings when fanins/fanouts are duplicated
set checkread # checks new networks after reading from file
set backup # saves backup networks retrived by "undo" and "recall"
set savesteps 1 # sets the maximum number of backup networks to save
set progressbar # display the progress bar
# program names for internal calls
set dotwin dot.exe
set dotunix dot
set gsviewwin gsview32.exe
set gsviewunix gv
set siswin sis.exe
set sisunix sis
set mvsiswin mvsis.exe
set mvsisunix mvsis
set capowin MetaPl-Capo10.1-Win32.exe
set capounix MetaPl-Capo10.1
set gnuplotwin wgnuplot.exe
set gnuplotunix gnuplot
# standard aliases
alias b balance
alias cl cleanup
alias clp collapse
alias esd ext_seq_dcs
alias f fraig
alias fs fraig_sweep
alias fsto fraig_store
alias fres fraig_restore
alias ft fraig_trust
alias lp lutpack
alias pd print_dsd
alias pex print_exdc -d
alias pf print_factor
alias pfan print_fanio
alias pl print_level
alias pio print_io
alias pk print_kmap
alias ps print_stats
alias psu print_supp
alias psy print_symm
alias pun print_unate
alias q quit
alias r read
alias r3 retime -M 3
alias r3f retime -M 3 -f
alias r3b retime -M 3 -b
alias ren renode
alias rh read_hie
alias rl read_blif
alias rb read_bench
alias ret retime
alias rp read_pla
alias rt read_truth
alias rv read_verilog
alias rvl read_verlib
alias rsup read_super mcnc5_old.super
alias rlib read_library
alias rlibc read_library cadence.genlib
alias rw rewrite
alias rwz rewrite -z
alias rf refactor
alias rfz refactor -z
alias re restructure
alias rez restructure -z
alias rs resub
alias rsz resub -z
alias sa set autoexec ps
alias scl scleanup
alias sif if -s
alias so source -x
alias st strash
alias sw sweep
alias ssw ssweep
alias tr0 trace_start
alias tr1 trace_check
alias trt "r c.blif; st; tr0; b; tr1"
alias u undo
alias w write
alias wa write_aiger
alias wb write_bench
alias wc write_cnf
alias wh write_hie
alias wl write_blif
alias wp write_pla
alias wv write_verilog
# standard scripts
alias share "b; ren -s; fx; b"
alias sharedsd "b; ren -b; dsd -g; sw; fx; b"
alias resyn "b; rw; rwz; b; rwz; b"
alias resyn2 "b; rw; rf; b; rw; rwz; b; rfz; rwz; b"
alias resyn2a "b; rw; b; rw; rwz; b; rwz; b"
alias resyn3 "b; rs; rs -K 6; b; rsz; rsz -K 6; b; rsz -K 5; b"
alias compress "b -l; rw -l; rwz -l; b -l; rwz -l; b -l"
alias compress2 "b -l; rw -l; rf -l; b -l; rw -l; rwz -l; b -l; rfz -l; rwz -l; b -l"
alias choice "fraig_store; resyn; fraig_store; resyn2; fraig_store; fraig_restore"
alias choice2 "fraig_store; balance; fraig_store; resyn; fraig_store; resyn2; fraig_store; resyn2; fraig_store; fraig_restore"
alias rwsat "st; rw -l; b -l; rw -l; rf -l"
alias rwsat2 "st; rw -l; b -l; rw -l; rf -l; fraig; rw -l; b -l; rw -l; rf -l"
alias shake "st; ps; sat -C 5000; rw -l; ps; sat -C 5000; b -l; rf -l; ps; sat -C 5000; rfz -l; ps; sat -C 5000; rwz -l; ps; sat -C 5000; rfz -l; ps; sat -C 5000"
# resubstitution scripts for the IWLS paper
alias src_rw "st; rw -l; rwz -l; rwz -l"
alias src_rs "st; rs -K 6 -N 2 -l; rs -K 9 -N 2 -l; rs -K 12 -N 2 -l"
alias src_rws "st; rw -l; rs -K 6 -N 2 -l; rwz -l; rs -K 9 -N 2 -l; rwz -l; rs -K 12 -N 2 -l"
alias resyn2rs "b; rs -K 6; rw; rs -K 6 -N 2; rf; rs -K 8; b; rs -K 8 -N 2; rw; rs -K 10; rwz; rs -K 10 -N 2; b; rs -K 12; rfz; rs -K 12 -N 2; rwz; b"
alias compress2rs "b -l; rs -K 6 -l; rw -l; rs -K 6 -N 2 -l; rf -l; rs -K 8 -l; b -l; rs -K 8 -N 2 -l; rw -l; rs -K 10 -l; rwz -l; rs -K 10 -N 2 -l; b -l; rs -K 12 -l; rfz -l; rs -K 12 -N 2 -l; rwz -l; b -l"
# experimental implementation of don't-cares
alias resyn2rsdc "b; rs -K 6 -F 2; rw; rs -K 6 -N 2 -F 2; rf; rs -K 8 -F 2; b; rs -K 8 -N 2 -F 2; rw; rs -K 10 -F 2; rwz; rs -K 10 -N 2 -F 2; b; rs -K 12 -F 2; rfz; rs -K 12 -N 2 -F 2; rwz; b"
alias compress2rsdc "b -l; rs -K 6 -F 2 -l; rw -l; rs -K 6 -N 2 -F 2 -l; rf -l; rs -K 8 -F 2 -l; b -l; rs -K 8 -N 2 -F 2 -l; rw -l; rs -K 10 -F 2 -l; rwz -l; rs -K 10 -N 2 -F 2 -l; b -l; rs -K 12 -F 2 -l; rfz -l; rs -K 12 -N 2 -F 2 -l; rwz -l; b -l"
# minimizing for FF literals
alias fflitmin "compress2rs; ren; sop; ps -f"
# temporaries
#alias t "rvl th/lib.v; rvv th/t2.v"
#alias t "so c/pure_sat/test.c"
#alias t "r c/14/csat_998.bench; st; ps"
#alias t0 "r res.blif; aig; mfs"
#alias t "r res2.blif; aig; mfs"
#alias tt "r a/quip_opt/nut_001_opt.blif"
#alias ttb "wh a/quip_opt/nut_001_opt.blif 1.blif"
#alias ttv "wh a/quip_opt/nut_001_opt.blif 1.v"
alias reach "st; ps; compress2; ps; qrel; ps; compress2; ps; qreach -v; ps"
alias qs1 "qvar -I 96 -u; ps; qbf -P 96"
alias qs2 "qvar -I 96 -u; qvar -I 97 -u; ps; qbf -P 96"
alias qs3 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; ps; qbf -P 96"
alias qs4 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; ps; qbf -P 96"
alias qs5 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; ps; qbf -P 96"
alias qs6 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; ps; qbf -P 96"
alias qs7 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; ps; qbf -P 96"
alias qs8 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; ps; qbf -P 96"
alias qs9 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; qvar -I 104 -u; ps; qbf -P 96"
alias qsA "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; qvar -I 104 -u; qvar -I 105 -u; ps; qbf -P 96"
alias chnew "st; haig_start; resyn2; haig_use"
alias chnewrs "st; haig_start; resyn2rs; haig_use"
alias stdsd "r test/6in.blif; st; ps; u; bdd; dsd -g; st; ps"
alias trec "rec_start; r c.blif; st; rec_add; rec_use"
alias trec4 "rec_start -K 4; r i10.blif; st; rec_add; rec_use"
alias trec5 "rec_start -K 5; r i10.blif; st; rec_add; rec_use"
alias trec6 "rec_start -K 6; r i10.blif; st; rec_add; rec_use"
alias trec7 "rec_start -K 7; r i10.blif; st; rec_add; rec_use"
alias trec8 "rec_start -K 8; r i10.blif; st; rec_add; rec_use"
alias trec10 "rec_start -K 10; r i10.blif; st; rec_add; rec_use"
alias trec12 "rec_start -K 12; r i10.blif; st; rec_add; rec_use"
#alias tsh "r i10_if.blif; st; ps; u; sw; st; ps; cec"
alias tst4 "r i10_if4.blif; st; ps; r x/rec4_.blif; st; rec_start; r i10_if4.blif; st -r; ps; cec"
alias tst4n "r i10_if4.blif; st; ps; r 5npn/all_functions.aig; st; rec_start; r i10_if4.blif; st -r; ps; cec"
alias tst6 "r i10_if6.blif; st; ps; r x/rec6_16_.blif; st; rec_start; r i10_if6.blif; st -r; ps; cec"
#alias t "r c.blif; st; wc c.cnf"
#alias t "r test/dsdmap6.blif; lutpack -vw; cec"
#alias t "r i10_if4.blif; lp"
#alias t1 "r pj1_if4.blif; lp"
#alias t2 "r pj1_if6.blif; lp"
#alias t "r pj/pj1.blif; st; dfraig -v"
#alias t "r c/16/csat_2.bench; st; dfraig -C 100 -v -r"
#alias t "r c/16/csat_147.bench; st; dfraig -C 10 -v -r"
#alias t "r i10.blif; st; ps; csweep; ps; cec"
#alias t "r c/5/csat_777.bench; st; csweep -v"
#alias t "r i10.blif; st; drw -v"
alias t "r c.blif; st; drf"
regression/issue_00174/abc.tcl 0 → 100644
source abc.rc;
print_lut;
resyn;
regression/issue_00174/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [5:0] o;
reg [5:0] i;
wire [5:0] wave_out;
always @(posedge clk)
i <= i + 1;
wire [31:0] w = 1-i;
assign wave_out = w/2;
top uut (i,o);
genvar index;
generate
for (index=0; index <= 2; index=index+1)
begin: gen_code_label
assert_dff check_output(clk,o[index],wave_out[index]);
end
endgenerate
endmodule
regression/issue_00174/top.v 0 → 100644
module top
(
input [5:0] ptr,
output [5:0] wave_out
);
wire [31:0] w = 1-ptr;
assign wave_out = w/2;
endmodule
regression/issue_00175/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire GC;
wire GC_p;
reg E = 0;
always @(posedge clk)
E = ~E;
reg ED;
always@(*) begin
if(~clk)
ED = E;
end
assign GC_p = clk & ED;
top uut (clk,CG,E);
assert_dff check_output(clk,GC,GC_p);
endmodule
regression/issue_00175/top.v 0 → 100644
module top (
C,
GC,
E
);
input C;
output GC;
input E;
reg ED;
always@(*) begin
if(~C)
ED = E;
end
assign GC = C & ED;
endmodule
regression/issue_00182/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
endmodule
regression/issue_00182/top.v 0 → 100644
/* Machine-generated using LiteX gen */
module top(
output reg serial_tx,
input serial_rx,
output MOTEA,
output DRVSA,
output STEP,
output DIR,
output WDATA,
output WGATE,
input TRK00,
output user_led,
input WPT,
output user_led_1,
output SIDE1,
input INDEX,
input RDATA,
output reg user_led_2,
output reg user_led_3,
input clk50
);
wire [29:0] ibm360dd_sram_bus_adr;
wire [31:0] ibm360dd_sram_bus_dat_w;
wire [31:0] ibm360dd_sram_bus_dat_r;
wire [3:0] ibm360dd_sram_bus_sel;
wire ibm360dd_sram_bus_cyc;
wire ibm360dd_sram_bus_stb;
reg ibm360dd_sram_bus_ack = 1'd0;
wire ibm360dd_sram_bus_we;
wire [2:0] ibm360dd_sram_bus_cti;
wire [1:0] ibm360dd_sram_bus_bte;
reg ibm360dd_sram_bus_err = 1'd0;
wire [9:0] ibm360dd_sram_adr;
wire [31:0] ibm360dd_sram_dat_r;
reg [3:0] ibm360dd_sram_we = 1'd0;
wire [31:0] ibm360dd_sram_dat_w;
reg [13:0] ibm360dd_interface_adr = 1'd0;
reg ibm360dd_interface_we = 1'd0;
reg [31:0] ibm360dd_interface_dat_w = 1'd0;
wire [31:0] ibm360dd_interface_dat_r;
wire [29:0] ibm360dd_bus_wishbone_adr;
wire [31:0] ibm360dd_bus_wishbone_dat_w;
reg [31:0] ibm360dd_bus_wishbone_dat_r = 1'd0;
wire [3:0] ibm360dd_bus_wishbone_sel;
wire ibm360dd_bus_wishbone_cyc;
wire ibm360dd_bus_wishbone_stb;
reg ibm360dd_bus_wishbone_ack = 1'd0;
wire ibm360dd_bus_wishbone_we;
wire [2:0] ibm360dd_bus_wishbone_cti;
wire [1:0] ibm360dd_bus_wishbone_bte;
reg ibm360dd_bus_wishbone_err = 1'd0;
reg [1:0] ibm360dd_counter = 1'd0;
reg [31:0] ibm360dd_storage = 24'd9895604;
reg ibm360dd_sink_valid = 1'd0;
reg ibm360dd_sink_ready = 1'd0;
wire ibm360dd_sink_last;
reg [7:0] ibm360dd_sink_payload_data = 1'd0;
reg ibm360dd_uart_clk_txen = 1'd0;
reg [31:0] ibm360dd_phase_accumulator_tx = 1'd0;
reg [7:0] ibm360dd_tx_reg = 1'd0;
reg [3:0] ibm360dd_tx_bitcount = 1'd0;
reg ibm360dd_tx_busy = 1'd0;
reg ibm360dd_source_valid = 1'd0;
wire ibm360dd_source_ready;
reg [7:0] ibm360dd_source_payload_data = 1'd0;
reg ibm360dd_uart_clk_rxen = 1'd0;
reg [31:0] ibm360dd_phase_accumulator_rx = 1'd0;
wire ibm360dd_rx;
reg ibm360dd_rx_r = 1'd0;
reg [7:0] ibm360dd_rx_reg = 1'd0;
reg [3:0] ibm360dd_rx_bitcount = 1'd0;
reg ibm360dd_rx_busy = 1'd0;
wire [29:0] ibm360dd_wishbone_adr;
wire [31:0] ibm360dd_wishbone_dat_w;
wire [31:0] ibm360dd_wishbone_dat_r;
wire [3:0] ibm360dd_wishbone_sel;
reg ibm360dd_wishbone_cyc = 1'd0;
reg ibm360dd_wishbone_stb = 1'd0;
wire ibm360dd_wishbone_ack;
reg ibm360dd_wishbone_we = 1'd0;
reg [2:0] ibm360dd_wishbone_cti = 1'd0;
reg [1:0] ibm360dd_wishbone_bte = 1'd0;
wire ibm360dd_wishbone_err;
reg [2:0] ibm360dd_byte_counter = 1'd0;
reg ibm360dd_byte_counter_reset = 1'd0;
reg ibm360dd_byte_counter_ce = 1'd0;
reg [2:0] ibm360dd_word_counter = 1'd0;
reg ibm360dd_word_counter_reset = 1'd0;
reg ibm360dd_word_counter_ce = 1'd0;
reg [7:0] ibm360dd_cmd = 1'd0;
reg ibm360dd_cmd_ce = 1'd0;
reg [7:0] ibm360dd_length = 1'd0;
reg ibm360dd_length_ce = 1'd0;
reg [31:0] ibm360dd_address = 1'd0;
reg ibm360dd_address_ce = 1'd0;
reg [31:0] ibm360dd_data = 1'd0;
reg ibm360dd_rx_data_ce = 1'd0;
reg ibm360dd_tx_data_ce = 1'd0;
wire ibm360dd_reset;
wire ibm360dd_wait;
wire ibm360dd_done;
reg [22:0] ibm360dd_count = 23'd5000000;
reg ibm360dd_is_ongoing = 1'd0;
reg [8:0] io_status;// = 1'd0;
reg [8:0] io_storage_full = 9'd511;
wire [8:0] io_storage;
reg io_re = 1'd0;
reg [3:0] sigs_counter = 1'd0;
reg sigs_index_edge = 1'd0;
reg sigs_latched_index = 1'd0;
reg [18:0] sigs_dat_counter = 1'd0;
reg sigs_data_edge = 1'd0;
reg sigs_latched_data = 1'd0;
wire frontend_sink_sink_valid;
wire frontend_sink_sink_ready;
reg frontend_sink_sink_last = 1'd0;
wire [1:0] frontend_sink_sink_payload_data;
reg frontend_sink_sink_payload_hit = 1'd0;
wire frontend_source_source_valid;
wire frontend_source_source_ready;
wire frontend_source_source_last;
wire [1:0] frontend_source_source_payload_data;
wire frontend_source_source_payload_hit;
wire frontend_buffer_sink_valid;
wire frontend_buffer_sink_ready;
wire frontend_buffer_sink_last;
wire [1:0] frontend_buffer_sink_payload_data;
wire frontend_buffer_sink_payload_hit;
wire frontend_buffer_source_valid;
wire frontend_buffer_source_ready;
wire frontend_buffer_source_last;
reg [1:0] frontend_buffer_source_payload_data = 1'd0;
reg frontend_buffer_source_payload_hit = 1'd0;
wire frontend_buffer_pipe_ce;
reg frontend_buffer_valid_n = 1'd0;
reg frontend_buffer_last_n = 1'd0;
wire frontend_trigger_sink_valid;
wire frontend_trigger_sink_ready;
wire frontend_trigger_sink_last;
wire [1:0] frontend_trigger_sink_payload_data;
wire frontend_trigger_sink_payload_hit;
wire frontend_trigger_source_valid;
wire frontend_trigger_source_ready;
wire frontend_trigger_source_last;
wire [1:0] frontend_trigger_source_payload_data;
reg frontend_trigger_source_payload_hit = 1'd0;
reg [1:0] frontend_trigger_value_storage_full = 1'd0;
wire [1:0] frontend_trigger_value_storage;
reg frontend_trigger_value_re = 1'd0;
reg [1:0] frontend_trigger_mask_storage_full = 1'd0;
wire [1:0] frontend_trigger_mask_storage;
reg frontend_trigger_mask_re = 1'd0;
wire [1:0] frontend_trigger_value;
wire [1:0] frontend_trigger_mask;
wire frontend_subsampler_sink_valid;
wire frontend_subsampler_sink_ready;
wire frontend_subsampler_sink_last;
wire [1:0] frontend_subsampler_sink_payload_data;
wire frontend_subsampler_sink_payload_hit;
wire frontend_subsampler_source_valid;
wire frontend_subsampler_source_ready;
wire frontend_subsampler_source_last;
wire [1:0] frontend_subsampler_source_payload_data;
wire frontend_subsampler_source_payload_hit;
reg [15:0] frontend_subsampler_value_storage_full = 1'd0;
wire [15:0] frontend_subsampler_value_storage;
reg frontend_subsampler_value_re = 1'd0;
wire [15:0] frontend_subsampler_value;
reg [15:0] frontend_subsampler_counter = 1'd0;
wire frontend_subsampler_done;
wire frontend_strideconverter_sink_valid;
wire frontend_strideconverter_sink_ready;
wire frontend_strideconverter_sink_last;
wire [1:0] frontend_strideconverter_sink_payload_data;
wire frontend_strideconverter_sink_payload_hit;
wire frontend_strideconverter_source_valid;
wire frontend_strideconverter_source_ready;
wire frontend_strideconverter_source_last;
wire [1:0] frontend_strideconverter_source_payload_data;
wire frontend_strideconverter_source_payload_hit;
wire frontend_strideconverter_converter_sink_valid;
wire frontend_strideconverter_converter_sink_ready;
wire frontend_strideconverter_converter_sink_last;
wire [2:0] frontend_strideconverter_converter_sink_payload_data;
wire frontend_strideconverter_converter_source_valid;
wire frontend_strideconverter_converter_source_ready;
wire frontend_strideconverter_converter_source_last;
wire [2:0] frontend_strideconverter_converter_source_payload_data;
wire frontend_strideconverter_converter_source_payload_valid_token_count;
wire frontend_strideconverter_source_source_valid;
wire frontend_strideconverter_source_source_ready;
wire frontend_strideconverter_source_source_last;
wire [2:0] frontend_strideconverter_source_source_payload_data;
wire frontend_asyncfifo_sink_valid;
wire frontend_asyncfifo_sink_ready;
wire frontend_asyncfifo_sink_last;
wire [1:0] frontend_asyncfifo_sink_payload_data;
wire frontend_asyncfifo_sink_payload_hit;
wire frontend_asyncfifo_source_valid;
wire frontend_asyncfifo_source_ready;
wire frontend_asyncfifo_source_last;
wire [1:0] frontend_asyncfifo_source_payload_data;
wire frontend_asyncfifo_source_payload_hit;
wire frontend_asyncfifo_asyncfifo_we;
wire frontend_asyncfifo_asyncfifo_writable;
wire frontend_asyncfifo_asyncfifo_re;
wire frontend_asyncfifo_asyncfifo_readable;
wire [3:0] frontend_asyncfifo_asyncfifo_din;
wire [3:0] frontend_asyncfifo_asyncfifo_dout;
wire frontend_asyncfifo_graycounter0_ce;
reg [3:0] frontend_asyncfifo_graycounter0_q = 1'd0;
wire [3:0] frontend_asyncfifo_graycounter0_q_next;
reg [3:0] frontend_asyncfifo_graycounter0_q_binary = 1'd0;
reg [3:0] frontend_asyncfifo_graycounter0_q_next_binary = 1'd0;
wire frontend_asyncfifo_graycounter1_ce;
reg [3:0] frontend_asyncfifo_graycounter1_q = 1'd0;
wire [3:0] frontend_asyncfifo_graycounter1_q_next;
reg [3:0] frontend_asyncfifo_graycounter1_q_binary = 1'd0;
reg [3:0] frontend_asyncfifo_graycounter1_q_next_binary = 1'd0;
wire [3:0] frontend_asyncfifo_produce_rdomain;
wire [3:0] frontend_asyncfifo_consume_wdomain;
wire [2:0] frontend_asyncfifo_wrport_adr;
wire [3:0] frontend_asyncfifo_wrport_dat_r;
wire frontend_asyncfifo_wrport_we;
wire [3:0] frontend_asyncfifo_wrport_dat_w;
wire [2:0] frontend_asyncfifo_rdport_adr;
wire [3:0] frontend_asyncfifo_rdport_dat_r;
wire [1:0] frontend_asyncfifo_fifo_in_payload_data;
wire frontend_asyncfifo_fifo_in_payload_hit;
wire frontend_asyncfifo_fifo_in_last;
wire [1:0] frontend_asyncfifo_fifo_out_payload_data;
wire frontend_asyncfifo_fifo_out_payload_hit;
wire frontend_asyncfifo_fifo_out_last;
wire storage_sink_sink_valid;
reg storage_sink_sink_ready = 1'd0;
wire storage_sink_sink_last;
wire [1:0] storage_sink_sink_payload_data;
wire storage_sink_sink_payload_hit;
wire storage_start_re;
wire storage_start_r;
reg storage_start_w = 1'd0;
reg [14:0] storage_length_storage_full = 1'd0;
wire [14:0] storage_length_storage;
reg storage_length_re = 1'd0;
reg [14:0] storage_offset_storage_full = 1'd0;
wire [14:0] storage_offset_storage;
reg storage_offset_re = 1'd0;
reg storage_idle_status = 1'd0;
reg storage_wait_status = 1'd0;
reg storage_run_status = 1'd0;
wire storage_mem_valid_status;
wire storage_mem_ready_re;
wire storage_mem_ready_r;
reg storage_mem_ready_w = 1'd0;
wire [1:0] storage_mem_data_status;
reg storage_mem_sink_valid = 1'd0;
wire storage_mem_sink_ready;
reg storage_mem_sink_last = 1'd0;
reg [1:0] storage_mem_sink_payload_data = 1'd0;
wire storage_mem_source_valid;
reg storage_mem_source_ready = 1'd0;
wire storage_mem_source_last;
wire [1:0] storage_mem_source_payload_data;
wire storage_mem_re;
reg storage_mem_readable = 1'd0;
wire storage_mem_syncfifo_we;
wire storage_mem_syncfifo_writable;
wire storage_mem_syncfifo_re;
wire storage_mem_syncfifo_readable;
wire [2:0] storage_mem_syncfifo_din;
wire [2:0] storage_mem_syncfifo_dout;
reg [14:0] storage_mem_level0 = 1'd0;
reg storage_mem_replace = 1'd0;
reg [13:0] storage_mem_produce = 1'd0;
reg [13:0] storage_mem_consume = 1'd0;
reg [13:0] storage_mem_wrport_adr = 1'd0;
wire [2:0] storage_mem_wrport_dat_r;
wire storage_mem_wrport_we;
wire [2:0] storage_mem_wrport_dat_w;
wire storage_mem_do_read;
wire [13:0] storage_mem_rdport_adr;
wire [2:0] storage_mem_rdport_dat_r;
wire storage_mem_rdport_re;
wire [14:0] storage_mem_level1;
wire [1:0] storage_mem_fifo_in_payload_data;
wire storage_mem_fifo_in_last;
wire [1:0] storage_mem_fifo_out_payload_data;
wire storage_mem_fifo_out_last;
reg [2:0] uartwishbonebridge_state = 1'd0;
reg [2:0] uartwishbonebridge_next_state = 1'd0;
reg [1:0] litescopeanalyzer_state = 1'd0;
reg [1:0] litescopeanalyzer_next_state = 1'd0;
wire [29:0] shared_adr;
wire [31:0] shared_dat_w;
wire [31:0] shared_dat_r;
wire [3:0] shared_sel;
wire shared_cyc;
wire shared_stb;
wire shared_ack;
wire shared_we;
wire [2:0] shared_cti;
wire [1:0] shared_bte;
wire shared_err;
wire request;
wire grant;
reg [1:0] slave_sel = 1'd0;
reg [1:0] slave_sel_r = 1'd0;
wire [13:0] interface0_adr;
wire interface0_we;
wire [31:0] interface0_dat_w;
reg [31:0] interface0_dat_r = 1'd0;
wire csrbank0_frontend_trigger_value0_re;
wire [1:0] csrbank0_frontend_trigger_value0_r;
wire [1:0] csrbank0_frontend_trigger_value0_w;
wire csrbank0_frontend_trigger_mask0_re;
wire [1:0] csrbank0_frontend_trigger_mask0_r;
wire [1:0] csrbank0_frontend_trigger_mask0_w;
wire csrbank0_frontend_subsampler_value0_re;
wire [15:0] csrbank0_frontend_subsampler_value0_r;
wire [15:0] csrbank0_frontend_subsampler_value0_w;
wire csrbank0_storage_length0_re;
wire [14:0] csrbank0_storage_length0_r;
wire [14:0] csrbank0_storage_length0_w;
wire csrbank0_storage_offset0_re;
wire [14:0] csrbank0_storage_offset0_r;
wire [14:0] csrbank0_storage_offset0_w;
wire csrbank0_storage_idle_re;
wire csrbank0_storage_idle_r;
wire csrbank0_storage_idle_w;
wire csrbank0_storage_wait_re;
wire csrbank0_storage_wait_r;
wire csrbank0_storage_wait_w;
wire csrbank0_storage_run_re;
wire csrbank0_storage_run_r;
wire csrbank0_storage_run_w;
wire csrbank0_storage_mem_valid_re;
wire csrbank0_storage_mem_valid_r;
wire csrbank0_storage_mem_valid_w;
wire csrbank0_storage_mem_data_re;
wire [1:0] csrbank0_storage_mem_data_r;
wire [1:0] csrbank0_storage_mem_data_w;
wire csrbank0_sel;
wire [13:0] interface1_adr;
wire interface1_we;
wire [31:0] interface1_dat_w;
reg [31:0] interface1_dat_r = 1'd0;
wire [4:0] mmap_adr;
wire [7:0] mmap_dat_r;
wire mmap_sel;
reg mmap_sel_r = 1'd0;
wire [13:0] interface2_adr;
wire interface2_we;
wire [31:0] interface2_dat_w;
reg [31:0] interface2_dat_r = 1'd0;
wire csrbank1_input_re;
wire [8:0] csrbank1_input_r;
wire [8:0] csrbank1_input_w;
wire csrbank1_output0_re;
wire [8:0] csrbank1_output0_r;
wire [8:0] csrbank1_output0_w;
wire csrbank1_sel;
wire sys_clk;
wire sys_rst;
wire por_clk;
reg int_rst = 1'd1;
reg [29:0] array_muxed0 = 1'd0;
reg [31:0] array_muxed1 = 1'd0;
reg [3:0] array_muxed2 = 1'd0;
reg array_muxed3 = 1'd0;
reg array_muxed4 = 1'd0;
reg array_muxed5 = 1'd0;
reg [2:0] array_muxed6 = 1'd0;
reg [1:0] array_muxed7 = 1'd0;
reg xilinxmultiregvivadoimpl0_regs0 = 1'd0;
reg xilinxmultiregvivadoimpl0_regs1 = 1'd0;
reg [1:0] xilinxmultiregvivadoimpl1_regs0 = 1'd0;
reg [1:0] xilinxmultiregvivadoimpl1_regs1 = 1'd0;
reg [1:0] xilinxmultiregvivadoimpl2_regs0 = 1'd0;
reg [1:0] xilinxmultiregvivadoimpl2_regs1 = 1'd0;
reg [15:0] xilinxmultiregvivadoimpl3_regs0 = 1'd0;
reg [15:0] xilinxmultiregvivadoimpl3_regs1 = 1'd0;
reg [3:0] xilinxmultiregvivadoimpl4_regs0 = 1'd0;
reg [3:0] xilinxmultiregvivadoimpl4_regs1 = 1'd0;
reg [3:0] xilinxmultiregvivadoimpl5_regs0 = 1'd0;
reg [3:0] xilinxmultiregvivadoimpl5_regs1 = 1'd0;
// synthesis translate_off
reg dummy_s;
initial dummy_s <= 1'd0;
// synthesis translate_on
assign MOTEA = io_storage[0];
assign DRVSA = io_storage[1];
assign STEP = io_storage[2];
assign DIR = io_storage[3];
assign WDATA = io_storage[4];
assign WGATE = io_storage[5];
assign user_led = (~TRK00);
assign user_led_1 = (~WPT);
assign SIDE1 = io_storage[8];
// synthesis translate_off
reg dummy_d;
// synthesis translate_on
always @(*) begin
io_status <= 1'd0;
io_status[0] <= MOTEA;
io_status[1] <= DRVSA;
io_status[2] <= STEP;
io_status[3] <= DIR;
io_status[4] <= WDATA;
io_status[5] <= WGATE;
io_status[6] <= TRK00;
io_status[7] <= WPT;
io_status[8] <= SIDE1;
// synthesis translate_off
dummy_d <= dummy_s;
// synthesis translate_on
end
// synthesis translate_off
reg dummy_d_1;
// synthesis translate_on
always @(*) begin
ibm360dd_sram_we <= 1'd0;
ibm360dd_sram_we[0] <= (((ibm360dd_sram_bus_cyc & ibm360dd_sram_bus_stb) & ibm360dd_sram_bus_we) & ibm360dd_sram_bus_sel[0]);
ibm360dd_sram_we[1] <= (((ibm360dd_sram_bus_cyc & ibm360dd_sram_bus_stb) & ibm360dd_sram_bus_we) & ibm360dd_sram_bus_sel[1]);
ibm360dd_sram_we[2] <= (((ibm360dd_sram_bus_cyc & ibm360dd_sram_bus_stb) & ibm360dd_sram_bus_we) & ibm360dd_sram_bus_sel[2]);
ibm360dd_sram_we[3] <= (((ibm360dd_sram_bus_cyc & ibm360dd_sram_bus_stb) & ibm360dd_sram_bus_we) & ibm360dd_sram_bus_sel[3]);
// synthesis translate_off
dummy_d_1 <= dummy_s;
// synthesis translate_on
end
assign ibm360dd_sram_adr = ibm360dd_sram_bus_adr[9:0];
assign ibm360dd_sram_bus_dat_r = ibm360dd_sram_dat_r;
assign ibm360dd_sram_dat_w = ibm360dd_sram_bus_dat_w;
assign ibm360dd_reset = ibm360dd_done;
assign ibm360dd_source_ready = 1'd1;
assign ibm360dd_wishbone_adr = (ibm360dd_address + ibm360dd_word_counter);
assign ibm360dd_wishbone_dat_w = ibm360dd_data;
assign ibm360dd_wishbone_sel = 4'd15;
// synthesis translate_off
reg dummy_d_2;
// synthesis translate_on
always @(*) begin
ibm360dd_sink_payload_data <= 1'd0;
case (ibm360dd_byte_counter)
1'd0: begin
ibm360dd_sink_payload_data <= ibm360dd_data[31:24];
end
1'd1: begin
ibm360dd_sink_payload_data <= ibm360dd_data[23:16];
end
2'd2: begin
ibm360dd_sink_payload_data <= ibm360dd_data[15:8];
end
default: begin
ibm360dd_sink_payload_data <= ibm360dd_data[7:0];
end
endcase
// synthesis translate_off
dummy_d_2 <= dummy_s;
// synthesis translate_on
end
assign ibm360dd_wait = (~ibm360dd_is_ongoing);
assign ibm360dd_sink_last = ((ibm360dd_byte_counter == 2'd3) & (ibm360dd_word_counter == (ibm360dd_length - 1'd1)));
// synthesis translate_off
reg dummy_d_3;
// synthesis translate_on
always @(*) begin
ibm360dd_length_ce <= 1'd0;
ibm360dd_wishbone_we <= 1'd0;
ibm360dd_address_ce <= 1'd0;
ibm360dd_rx_data_ce <= 1'd0;
ibm360dd_byte_counter_reset <= 1'd0;
ibm360dd_tx_data_ce <= 1'd0;
ibm360dd_byte_counter_ce <= 1'd0;
ibm360dd_word_counter_reset <= 1'd0;
ibm360dd_is_ongoing <= 1'd0;
ibm360dd_word_counter_ce <= 1'd0;
uartwishbonebridge_next_state <= 1'd0;
ibm360dd_sink_valid <= 1'd0;
ibm360dd_wishbone_cyc <= 1'd0;
ibm360dd_wishbone_stb <= 1'd0;
ibm360dd_cmd_ce <= 1'd0;
uartwishbonebridge_next_state <= uartwishbonebridge_state;
case (uartwishbonebridge_state)
1'd1: begin
if (ibm360dd_source_valid) begin
ibm360dd_length_ce <= 1'd1;
uartwishbonebridge_next_state <= 2'd2;
end
end
2'd2: begin
if (ibm360dd_source_valid) begin
ibm360dd_address_ce <= 1'd1;
ibm360dd_byte_counter_ce <= 1'd1;
if ((ibm360dd_byte_counter == 2'd3)) begin
if ((ibm360dd_cmd == 1'd1)) begin
uartwishbonebridge_next_state <= 2'd3;
end else begin
if ((ibm360dd_cmd == 2'd2)) begin
uartwishbonebridge_next_state <= 3'd5;
end
end
ibm360dd_byte_counter_reset <= 1'd1;
end
end
end
2'd3: begin
if (ibm360dd_source_valid) begin
ibm360dd_rx_data_ce <= 1'd1;
ibm360dd_byte_counter_ce <= 1'd1;
if ((ibm360dd_byte_counter == 2'd3)) begin
uartwishbonebridge_next_state <= 3'd4;
ibm360dd_byte_counter_reset <= 1'd1;
end
end
end
3'd4: begin
ibm360dd_wishbone_stb <= 1'd1;
ibm360dd_wishbone_we <= 1'd1;
ibm360dd_wishbone_cyc <= 1'd1;
if (ibm360dd_wishbone_ack) begin
ibm360dd_word_counter_ce <= 1'd1;
if ((ibm360dd_word_counter == (ibm360dd_length - 1'd1))) begin
uartwishbonebridge_next_state <= 1'd0;
end else begin
uartwishbonebridge_next_state <= 2'd3;
end
end
end
3'd5: begin
ibm360dd_wishbone_stb <= 1'd1;
ibm360dd_wishbone_we <= 1'd0;
ibm360dd_wishbone_cyc <= 1'd1;
if (ibm360dd_wishbone_ack) begin
ibm360dd_tx_data_ce <= 1'd1;
uartwishbonebridge_next_state <= 3'd6;
end
end
3'd6: begin
ibm360dd_sink_valid <= 1'd1;
if (ibm360dd_sink_ready) begin
ibm360dd_byte_counter_ce <= 1'd1;
if ((ibm360dd_byte_counter == 2'd3)) begin
ibm360dd_word_counter_ce <= 1'd1;
if ((ibm360dd_word_counter == (ibm360dd_length - 1'd1))) begin
uartwishbonebridge_next_state <= 1'd0;
end else begin
uartwishbonebridge_next_state <= 3'd5;
ibm360dd_byte_counter_reset <= 1'd1;
end
end
end
end
default: begin
if (ibm360dd_source_valid) begin
ibm360dd_cmd_ce <= 1'd1;
if (((ibm360dd_source_payload_data == 1'd1) | (ibm360dd_source_payload_data == 2'd2))) begin
uartwishbonebridge_next_state <= 1'd1;
end
ibm360dd_byte_counter_reset <= 1'd1;
ibm360dd_word_counter_reset <= 1'd1;
end
ibm360dd_is_ongoing <= 1'd1;
end
endcase
// synthesis translate_off
dummy_d_3 <= dummy_s;
// synthesis translate_on
end
assign ibm360dd_done = (ibm360dd_count == 1'd0);
assign frontend_sink_sink_valid = 1'd1;
assign frontend_sink_sink_payload_data = {RDATA, INDEX};
assign storage_sink_sink_valid = frontend_source_source_valid;
assign frontend_source_source_ready = storage_sink_sink_ready;
assign storage_sink_sink_last = frontend_source_source_last;
assign storage_sink_sink_payload_data = frontend_source_source_payload_data;
assign storage_sink_sink_payload_hit = frontend_source_source_payload_hit;
assign frontend_buffer_pipe_ce = (frontend_buffer_source_ready | (~frontend_buffer_valid_n));
assign frontend_buffer_sink_ready = frontend_buffer_pipe_ce;
assign frontend_buffer_source_valid = frontend_buffer_valid_n;
assign frontend_buffer_source_last = frontend_buffer_last_n;
assign frontend_trigger_source_valid = frontend_trigger_sink_valid;
assign frontend_trigger_sink_ready = frontend_trigger_source_ready;
assign frontend_trigger_source_last = frontend_trigger_sink_last;
assign frontend_trigger_source_payload_data = frontend_trigger_sink_payload_data;
// synthesis translate_off
reg dummy_d_4;
// synthesis translate_on
always @(*) begin
frontend_trigger_source_payload_hit <= 1'd0;
frontend_trigger_source_payload_hit <= frontend_trigger_sink_payload_hit;
frontend_trigger_source_payload_hit <= ((frontend_trigger_sink_payload_data & frontend_trigger_mask) == frontend_trigger_value);
// synthesis translate_off
dummy_d_4 <= dummy_s;
// synthesis translate_on
end
assign frontend_subsampler_done = (frontend_subsampler_counter == frontend_subsampler_value);
assign frontend_subsampler_sink_ready = frontend_subsampler_source_ready;
assign frontend_subsampler_source_last = frontend_subsampler_sink_last;
assign frontend_subsampler_source_payload_data = frontend_subsampler_sink_payload_data;
assign frontend_subsampler_source_payload_hit = frontend_subsampler_sink_payload_hit;
assign frontend_subsampler_source_valid = (frontend_subsampler_sink_valid & frontend_subsampler_done);
assign frontend_strideconverter_converter_sink_valid = frontend_strideconverter_sink_valid;
assign frontend_strideconverter_converter_sink_last = frontend_strideconverter_sink_last;
assign frontend_strideconverter_sink_ready = frontend_strideconverter_converter_sink_ready;
assign frontend_strideconverter_converter_sink_payload_data = {frontend_strideconverter_sink_payload_hit, frontend_strideconverter_sink_payload_data};
assign frontend_strideconverter_source_valid = frontend_strideconverter_source_source_valid;
assign frontend_strideconverter_source_last = frontend_strideconverter_source_source_last;
assign frontend_strideconverter_source_source_ready = frontend_strideconverter_source_ready;
assign {frontend_strideconverter_source_payload_hit, frontend_strideconverter_source_payload_data} = frontend_strideconverter_source_source_payload_data;
assign frontend_strideconverter_source_source_valid = frontend_strideconverter_converter_source_valid;
assign frontend_strideconverter_converter_source_ready = frontend_strideconverter_source_source_ready;
assign frontend_strideconverter_source_source_last = frontend_strideconverter_converter_source_last;
assign frontend_strideconverter_source_source_payload_data = frontend_strideconverter_converter_source_payload_data;
assign frontend_strideconverter_converter_source_valid = frontend_strideconverter_converter_sink_valid;
assign frontend_strideconverter_converter_sink_ready = frontend_strideconverter_converter_source_ready;
assign frontend_strideconverter_converter_source_last = frontend_strideconverter_converter_sink_last;
assign frontend_strideconverter_converter_source_payload_data = frontend_strideconverter_converter_sink_payload_data;
assign frontend_strideconverter_converter_source_payload_valid_token_count = 1'd1;
assign frontend_asyncfifo_asyncfifo_din = {frontend_asyncfifo_fifo_in_last, frontend_asyncfifo_fifo_in_payload_hit, frontend_asyncfifo_fifo_in_payload_data};
assign {frontend_asyncfifo_fifo_out_last, frontend_asyncfifo_fifo_out_payload_hit, frontend_asyncfifo_fifo_out_payload_data} = frontend_asyncfifo_asyncfifo_dout;
assign frontend_asyncfifo_sink_ready = frontend_asyncfifo_asyncfifo_writable;
assign frontend_asyncfifo_asyncfifo_we = frontend_asyncfifo_sink_valid;
assign frontend_asyncfifo_fifo_in_last = frontend_asyncfifo_sink_last;
assign frontend_asyncfifo_fifo_in_payload_data = frontend_asyncfifo_sink_payload_data;
assign frontend_asyncfifo_fifo_in_payload_hit = frontend_asyncfifo_sink_payload_hit;
assign frontend_asyncfifo_source_valid = frontend_asyncfifo_asyncfifo_readable;
assign frontend_asyncfifo_source_last = frontend_asyncfifo_fifo_out_last;
assign frontend_asyncfifo_source_payload_data = frontend_asyncfifo_fifo_out_payload_data;
assign frontend_asyncfifo_source_payload_hit = frontend_asyncfifo_fifo_out_payload_hit;
assign frontend_asyncfifo_asyncfifo_re = frontend_asyncfifo_source_ready;
assign frontend_asyncfifo_graycounter0_ce = (frontend_asyncfifo_asyncfifo_writable & frontend_asyncfifo_asyncfifo_we);
assign frontend_asyncfifo_graycounter1_ce = (frontend_asyncfifo_asyncfifo_readable & frontend_asyncfifo_asyncfifo_re);
assign frontend_asyncfifo_asyncfifo_writable = (((frontend_asyncfifo_graycounter0_q[3] == frontend_asyncfifo_consume_wdomain[3]) | (frontend_asyncfifo_graycounter0_q[2] == frontend_asyncfifo_consume_wdomain[2])) | (frontend_asyncfifo_graycounter0_q[1:0] != frontend_asyncfifo_consume_wdomain[1:0]));
assign frontend_asyncfifo_asyncfifo_readable = (frontend_asyncfifo_graycounter1_q != frontend_asyncfifo_produce_rdomain);
assign frontend_asyncfifo_wrport_adr = frontend_asyncfifo_graycounter0_q_binary[2:0];
assign frontend_asyncfifo_wrport_dat_w = frontend_asyncfifo_asyncfifo_din;
assign frontend_asyncfifo_wrport_we = frontend_asyncfifo_graycounter0_ce;
assign frontend_asyncfifo_rdport_adr = frontend_asyncfifo_graycounter1_q_next_binary[2:0];
assign frontend_asyncfifo_asyncfifo_dout = frontend_asyncfifo_rdport_dat_r;
// synthesis translate_off
reg dummy_d_5;
// synthesis translate_on
always @(*) begin
frontend_asyncfifo_graycounter0_q_next_binary <= 1'd0;
if (frontend_asyncfifo_graycounter0_ce) begin
frontend_asyncfifo_graycounter0_q_next_binary <= (frontend_asyncfifo_graycounter0_q_binary + 1'd1);
end else begin
frontend_asyncfifo_graycounter0_q_next_binary <= frontend_asyncfifo_graycounter0_q_binary;
end
// synthesis translate_off
dummy_d_5 <= dummy_s;
// synthesis translate_on
end
assign frontend_asyncfifo_graycounter0_q_next = (frontend_asyncfifo_graycounter0_q_next_binary ^ frontend_asyncfifo_graycounter0_q_next_binary[3:1]);
// synthesis translate_off
reg dummy_d_6;
// synthesis translate_on
always @(*) begin
frontend_asyncfifo_graycounter1_q_next_binary <= 1'd0;
if (frontend_asyncfifo_graycounter1_ce) begin
frontend_asyncfifo_graycounter1_q_next_binary <= (frontend_asyncfifo_graycounter1_q_binary + 1'd1);
end else begin
frontend_asyncfifo_graycounter1_q_next_binary <= frontend_asyncfifo_graycounter1_q_binary;
end
// synthesis translate_off
dummy_d_6 <= dummy_s;
// synthesis translate_on
end
assign frontend_asyncfifo_graycounter1_q_next = (frontend_asyncfifo_graycounter1_q_next_binary ^ frontend_asyncfifo_graycounter1_q_next_binary[3:1]);
assign frontend_buffer_sink_valid = frontend_sink_sink_valid;
assign frontend_sink_sink_ready = frontend_buffer_sink_ready;
assign frontend_buffer_sink_last = frontend_sink_sink_last;
assign frontend_buffer_sink_payload_data = frontend_sink_sink_payload_data;
assign frontend_buffer_sink_payload_hit = frontend_sink_sink_payload_hit;
assign frontend_trigger_sink_valid = frontend_buffer_source_valid;
assign frontend_buffer_source_ready = frontend_trigger_sink_ready;
assign frontend_trigger_sink_last = frontend_buffer_source_last;
assign frontend_trigger_sink_payload_data = frontend_buffer_source_payload_data;
assign frontend_trigger_sink_payload_hit = frontend_buffer_source_payload_hit;
assign frontend_subsampler_sink_valid = frontend_trigger_source_valid;
assign frontend_trigger_source_ready = frontend_subsampler_sink_ready;
assign frontend_subsampler_sink_last = frontend_trigger_source_last;
assign frontend_subsampler_sink_payload_data = frontend_trigger_source_payload_data;
assign frontend_subsampler_sink_payload_hit = frontend_trigger_source_payload_hit;
assign frontend_strideconverter_sink_valid = frontend_subsampler_source_valid;
assign frontend_subsampler_source_ready = frontend_strideconverter_sink_ready;
assign frontend_strideconverter_sink_last = frontend_subsampler_source_last;
assign frontend_strideconverter_sink_payload_data = frontend_subsampler_source_payload_data;
assign frontend_strideconverter_sink_payload_hit = frontend_subsampler_source_payload_hit;
assign frontend_asyncfifo_sink_valid = frontend_strideconverter_source_valid;
assign frontend_strideconverter_source_ready = frontend_asyncfifo_sink_ready;
assign frontend_asyncfifo_sink_last = frontend_strideconverter_source_last;
assign frontend_asyncfifo_sink_payload_data = frontend_strideconverter_source_payload_data;
assign frontend_asyncfifo_sink_payload_hit = frontend_strideconverter_source_payload_hit;
assign frontend_source_source_valid = frontend_asyncfifo_source_valid;
assign frontend_asyncfifo_source_ready = frontend_source_source_ready;
assign frontend_source_source_last = frontend_asyncfifo_source_last;
assign frontend_source_source_payload_data = frontend_asyncfifo_source_payload_data;
assign frontend_source_source_payload_hit = frontend_asyncfifo_source_payload_hit;
assign storage_mem_valid_status = storage_mem_source_valid;
assign storage_mem_data_status = storage_mem_source_payload_data;
assign storage_mem_syncfifo_din = {storage_mem_fifo_in_last, storage_mem_fifo_in_payload_data};
assign {storage_mem_fifo_out_last, storage_mem_fifo_out_payload_data} = storage_mem_syncfifo_dout;
assign storage_mem_sink_ready = storage_mem_syncfifo_writable;
assign storage_mem_syncfifo_we = storage_mem_sink_valid;
assign storage_mem_fifo_in_last = storage_mem_sink_last;
assign storage_mem_fifo_in_payload_data = storage_mem_sink_payload_data;
assign storage_mem_source_valid = storage_mem_readable;
assign storage_mem_source_last = storage_mem_fifo_out_last;
assign storage_mem_source_payload_data = storage_mem_fifo_out_payload_data;
assign storage_mem_re = storage_mem_source_ready;
assign storage_mem_syncfifo_re = (storage_mem_syncfifo_readable & ((~storage_mem_readable) | storage_mem_re));
assign storage_mem_level1 = (storage_mem_level0 + storage_mem_readable);
// synthesis translate_off
reg dummy_d_7;
// synthesis translate_on
always @(*) begin
storage_mem_wrport_adr <= 1'd0;
if (storage_mem_replace) begin
storage_mem_wrport_adr <= (storage_mem_produce - 1'd1);
end else begin
storage_mem_wrport_adr <= storage_mem_produce;
end
// synthesis translate_off
dummy_d_7 <= dummy_s;
// synthesis translate_on
end
assign storage_mem_wrport_dat_w = storage_mem_syncfifo_din;
assign storage_mem_wrport_we = (storage_mem_syncfifo_we & (storage_mem_syncfifo_writable | storage_mem_replace));
assign storage_mem_do_read = (storage_mem_syncfifo_readable & storage_mem_syncfifo_re);
assign storage_mem_rdport_adr = storage_mem_consume;
assign storage_mem_syncfifo_dout = storage_mem_rdport_dat_r;
assign storage_mem_rdport_re = storage_mem_do_read;
assign storage_mem_syncfifo_writable = (storage_mem_level0 != 15'd16384);
assign storage_mem_syncfifo_readable = (storage_mem_level0 != 1'd0);
// synthesis translate_off
reg dummy_d_8;
// synthesis translate_on
always @(*) begin
storage_mem_source_ready <= 1'd0;
storage_sink_sink_ready <= 1'd0;
storage_idle_status <= 1'd0;
storage_mem_sink_last <= 1'd0;
storage_wait_status <= 1'd0;
storage_run_status <= 1'd0;
storage_mem_sink_valid <= 1'd0;
litescopeanalyzer_next_state <= 1'd0;
storage_mem_sink_payload_data <= 1'd0;
litescopeanalyzer_next_state <= litescopeanalyzer_state;
case (litescopeanalyzer_state)
1'd1: begin
storage_wait_status <= 1'd1;
storage_mem_sink_valid <= storage_sink_sink_valid;
storage_sink_sink_ready <= storage_mem_sink_ready;
storage_mem_sink_last <= storage_sink_sink_last;
storage_mem_sink_payload_data <= storage_sink_sink_payload_data;
if ((storage_sink_sink_valid & (storage_sink_sink_payload_hit != 1'd0))) begin
litescopeanalyzer_next_state <= 2'd2;
end
storage_mem_source_ready <= (storage_mem_level1 >= storage_offset_storage);
end
2'd2: begin
storage_run_status <= 1'd1;
storage_mem_sink_valid <= storage_sink_sink_valid;
storage_sink_sink_ready <= storage_mem_sink_ready;
storage_mem_sink_last <= storage_sink_sink_last;
storage_mem_sink_payload_data <= storage_sink_sink_payload_data;
if (((~storage_mem_sink_ready) | (storage_mem_level1 >= storage_length_storage))) begin
litescopeanalyzer_next_state <= 1'd0;
storage_mem_source_ready <= 1'd1;
end
end
default: begin
storage_idle_status <= 1'd1;
if (storage_start_re) begin
litescopeanalyzer_next_state <= 1'd1;
end
storage_sink_sink_ready <= 1'd1;
storage_mem_source_ready <= (storage_mem_ready_re & storage_mem_ready_r);
end
endcase
// synthesis translate_off
dummy_d_8 <= dummy_s;
// synthesis translate_on
end
assign shared_adr = array_muxed0;
assign shared_dat_w = array_muxed1;
assign shared_sel = array_muxed2;
assign shared_cyc = array_muxed3;
assign shared_stb = array_muxed4;
assign shared_we = array_muxed5;
assign shared_cti = array_muxed6;
assign shared_bte = array_muxed7;
assign ibm360dd_wishbone_dat_r = shared_dat_r;
assign ibm360dd_wishbone_ack = (shared_ack & (grant == 1'd0));
assign ibm360dd_wishbone_err = (shared_err & (grant == 1'd0));
assign request = {ibm360dd_wishbone_cyc};
assign grant = 1'd0;
// synthesis translate_off
reg dummy_d_9;
// synthesis translate_on
always @(*) begin
slave_sel <= 1'd0;
slave_sel[0] <= (shared_adr[28:26] == 1'd1);
slave_sel[1] <= (shared_adr[28:26] == 3'd6);
// synthesis translate_off
dummy_d_9 <= dummy_s;
// synthesis translate_on
end
assign ibm360dd_sram_bus_adr = shared_adr;
assign ibm360dd_sram_bus_dat_w = shared_dat_w;
assign ibm360dd_sram_bus_sel = shared_sel;
assign ibm360dd_sram_bus_stb = shared_stb;
assign ibm360dd_sram_bus_we = shared_we;
assign ibm360dd_sram_bus_cti = shared_cti;
assign ibm360dd_sram_bus_bte = shared_bte;
assign ibm360dd_bus_wishbone_adr = shared_adr;
assign ibm360dd_bus_wishbone_dat_w = shared_dat_w;
assign ibm360dd_bus_wishbone_sel = shared_sel;
assign ibm360dd_bus_wishbone_stb = shared_stb;
assign ibm360dd_bus_wishbone_we = shared_we;
assign ibm360dd_bus_wishbone_cti = shared_cti;
assign ibm360dd_bus_wishbone_bte = shared_bte;
assign ibm360dd_sram_bus_cyc = (shared_cyc & slave_sel[0]);
assign ibm360dd_bus_wishbone_cyc = (shared_cyc & slave_sel[1]);
assign shared_ack = (ibm360dd_sram_bus_ack | ibm360dd_bus_wishbone_ack);
assign shared_err = (ibm360dd_sram_bus_err | ibm360dd_bus_wishbone_err);
assign shared_dat_r = (({32{slave_sel_r[0]}} & ibm360dd_sram_bus_dat_r) | ({32{slave_sel_r[1]}} & ibm360dd_bus_wishbone_dat_r));
assign csrbank0_sel = (interface0_adr[13:9] == 5'd17);
assign csrbank0_frontend_trigger_value0_r = interface0_dat_w[1:0];
assign csrbank0_frontend_trigger_value0_re = ((csrbank0_sel & interface0_we) & (interface0_adr[3:0] == 1'd0));
assign csrbank0_frontend_trigger_mask0_r = interface0_dat_w[1:0];
assign csrbank0_frontend_trigger_mask0_re = ((csrbank0_sel & interface0_we) & (interface0_adr[3:0] == 1'd1));
assign csrbank0_frontend_subsampler_value0_r = interface0_dat_w[15:0];
assign csrbank0_frontend_subsampler_value0_re = ((csrbank0_sel & interface0_we) & (interface0_adr[3:0] == 2'd2));
assign storage_start_r = interface0_dat_w[0];
assign storage_start_re = ((csrbank0_sel & interface0_we) & (interface0_adr[3:0] == 2'd3));
assign csrbank0_storage_length0_r = interface0_dat_w[14:0];
assign csrbank0_storage_length0_re = ((csrbank0_sel & interface0_we) & (interface0_adr[3:0] == 3'd4));
assign csrbank0_storage_offset0_r = interface0_dat_w[14:0];
assign csrbank0_storage_offset0_re = ((csrbank0_sel & interface0_we) & (interface0_adr[3:0] == 3'd5));
assign csrbank0_storage_idle_r = interface0_dat_w[0];
assign csrbank0_storage_idle_re = ((csrbank0_sel & interface0_we) & (interface0_adr[3:0] == 3'd6));
assign csrbank0_storage_wait_r = interface0_dat_w[0];
assign csrbank0_storage_wait_re = ((csrbank0_sel & interface0_we) & (interface0_adr[3:0] == 3'd7));
assign csrbank0_storage_run_r = interface0_dat_w[0];
assign csrbank0_storage_run_re = ((csrbank0_sel & interface0_we) & (interface0_adr[3:0] == 4'd8));
assign csrbank0_storage_mem_valid_r = interface0_dat_w[0];
assign csrbank0_storage_mem_valid_re = ((csrbank0_sel & interface0_we) & (interface0_adr[3:0] == 4'd9));
assign storage_mem_ready_r = interface0_dat_w[0];
assign storage_mem_ready_re = ((csrbank0_sel & interface0_we) & (interface0_adr[3:0] == 4'd10));
assign csrbank0_storage_mem_data_r = interface0_dat_w[1:0];
assign csrbank0_storage_mem_data_re = ((csrbank0_sel & interface0_we) & (interface0_adr[3:0] == 4'd11));
assign frontend_trigger_value_storage = frontend_trigger_value_storage_full[1:0];
assign csrbank0_frontend_trigger_value0_w = frontend_trigger_value_storage_full[1:0];
assign frontend_trigger_mask_storage = frontend_trigger_mask_storage_full[1:0];
assign csrbank0_frontend_trigger_mask0_w = frontend_trigger_mask_storage_full[1:0];
assign frontend_subsampler_value_storage = frontend_subsampler_value_storage_full[15:0];
assign csrbank0_frontend_subsampler_value0_w = frontend_subsampler_value_storage_full[15:0];
assign storage_length_storage = storage_length_storage_full[14:0];
assign csrbank0_storage_length0_w = storage_length_storage_full[14:0];
assign storage_offset_storage = storage_offset_storage_full[14:0];
assign csrbank0_storage_offset0_w = storage_offset_storage_full[14:0];
assign csrbank0_storage_idle_w = storage_idle_status;
assign csrbank0_storage_wait_w = storage_wait_status;
assign csrbank0_storage_run_w = storage_run_status;
assign csrbank0_storage_mem_valid_w = storage_mem_valid_status;
assign csrbank0_storage_mem_data_w = storage_mem_data_status[1:0];
assign mmap_sel = (interface1_adr[13:9] == 2'd3);
// synthesis translate_off
reg dummy_d_10;
// synthesis translate_on
always @(*) begin
interface1_dat_r <= 1'd0;
if (mmap_sel_r) begin
interface1_dat_r <= mmap_dat_r;
end
// synthesis translate_off
dummy_d_10 <= dummy_s;
// synthesis translate_on
end
assign mmap_adr = interface1_adr[4:0];
assign csrbank1_sel = (interface2_adr[13:9] == 5'd16);
assign csrbank1_input_r = interface2_dat_w[8:0];
assign csrbank1_input_re = ((csrbank1_sel & interface2_we) & (interface2_adr[0] == 1'd0));
assign csrbank1_output0_r = interface2_dat_w[8:0];
assign csrbank1_output0_re = ((csrbank1_sel & interface2_we) & (interface2_adr[0] == 1'd1));
assign csrbank1_input_w = io_status[8:0];
assign io_storage = io_storage_full[8:0];
assign csrbank1_output0_w = io_storage_full[8:0];
assign interface0_adr = ibm360dd_interface_adr;
assign interface2_adr = ibm360dd_interface_adr;
assign interface1_adr = ibm360dd_interface_adr;
assign interface0_we = ibm360dd_interface_we;
assign interface2_we = ibm360dd_interface_we;
assign interface1_we = ibm360dd_interface_we;
assign interface0_dat_w = ibm360dd_interface_dat_w;
assign interface2_dat_w = ibm360dd_interface_dat_w;
assign interface1_dat_w = ibm360dd_interface_dat_w;
assign ibm360dd_interface_dat_r = ((interface0_dat_r | interface2_dat_r) | interface1_dat_r);
assign sys_clk = clk50;
assign por_clk = clk50;
assign sys_rst = int_rst;
// synthesis translate_off
reg dummy_d_11;
// synthesis translate_on
always @(*) begin
array_muxed0 <= 1'd0;
case (grant)
default: begin
array_muxed0 <= ibm360dd_wishbone_adr;
end
endcase
// synthesis translate_off
dummy_d_11 <= dummy_s;
// synthesis translate_on
end
// synthesis translate_off
reg dummy_d_12;
// synthesis translate_on
always @(*) begin
array_muxed1 <= 1'd0;
case (grant)
default: begin
array_muxed1 <= ibm360dd_wishbone_dat_w;
end
endcase
// synthesis translate_off
dummy_d_12 <= dummy_s;
// synthesis translate_on
end
// synthesis translate_off
reg dummy_d_13;
// synthesis translate_on
always @(*) begin
array_muxed2 <= 1'd0;
case (grant)
default: begin
array_muxed2 <= ibm360dd_wishbone_sel;
end
endcase
// synthesis translate_off
dummy_d_13 <= dummy_s;
// synthesis translate_on
end
// synthesis translate_off
reg dummy_d_14;
// synthesis translate_on
always @(*) begin
array_muxed3 <= 1'd0;
case (grant)
default: begin
array_muxed3 <= ibm360dd_wishbone_cyc;
end
endcase
// synthesis translate_off
dummy_d_14 <= dummy_s;
// synthesis translate_on
end
// synthesis translate_off
reg dummy_d_15;
// synthesis translate_on
always @(*) begin
array_muxed4 <= 1'd0;
case (grant)
default: begin
array_muxed4 <= ibm360dd_wishbone_stb;
end
endcase
// synthesis translate_off
dummy_d_15 <= dummy_s;
// synthesis translate_on
end
// synthesis translate_off
reg dummy_d_16;
// synthesis translate_on
always @(*) begin
array_muxed5 <= 1'd0;
case (grant)
default: begin
array_muxed5 <= ibm360dd_wishbone_we;
end
endcase
// synthesis translate_off
dummy_d_16 <= dummy_s;
// synthesis translate_on
end
// synthesis translate_off
reg dummy_d_17;
// synthesis translate_on
always @(*) begin
array_muxed6 <= 1'd0;
case (grant)
default: begin
array_muxed6 <= ibm360dd_wishbone_cti;
end
endcase
// synthesis translate_off
dummy_d_17 <= dummy_s;
// synthesis translate_on
end
// synthesis translate_off
reg dummy_d_18;
// synthesis translate_on
always @(*) begin
array_muxed7 <= 1'd0;
case (grant)
default: begin
array_muxed7 <= ibm360dd_wishbone_bte;
end
endcase
// synthesis translate_off
dummy_d_18 <= dummy_s;
// synthesis translate_on
end
assign ibm360dd_rx = xilinxmultiregvivadoimpl0_regs1;
assign frontend_trigger_value = xilinxmultiregvivadoimpl1_regs1;
assign frontend_trigger_mask = xilinxmultiregvivadoimpl2_regs1;
assign frontend_subsampler_value = xilinxmultiregvivadoimpl3_regs1;
assign frontend_asyncfifo_produce_rdomain = xilinxmultiregvivadoimpl4_regs1;
assign frontend_asyncfifo_consume_wdomain = xilinxmultiregvivadoimpl5_regs1;
always @(posedge por_clk) begin
int_rst <= 1'd0;
end
always @(posedge sys_clk) begin
if (sys_rst) begin
ibm360dd_sram_bus_ack <= 1'd0;
ibm360dd_interface_adr <= 1'd0;
ibm360dd_interface_we <= 1'd0;
ibm360dd_interface_dat_w <= 1'd0;
ibm360dd_bus_wishbone_dat_r <= 1'd0;
ibm360dd_bus_wishbone_ack <= 1'd0;
ibm360dd_counter <= 1'd0;
serial_tx <= 1'd1;
ibm360dd_sink_ready <= 1'd0;
ibm360dd_uart_clk_txen <= 1'd0;
ibm360dd_phase_accumulator_tx <= 1'd0;
ibm360dd_tx_reg <= 1'd0;
ibm360dd_tx_bitcount <= 1'd0;
ibm360dd_tx_busy <= 1'd0;
ibm360dd_source_valid <= 1'd0;
ibm360dd_source_payload_data <= 1'd0;
ibm360dd_uart_clk_rxen <= 1'd0;
ibm360dd_phase_accumulator_rx <= 1'd0;
ibm360dd_rx_r <= 1'd0;
ibm360dd_rx_reg <= 1'd0;
ibm360dd_rx_bitcount <= 1'd0;
ibm360dd_rx_busy <= 1'd0;
ibm360dd_byte_counter <= 1'd0;
ibm360dd_word_counter <= 1'd0;
ibm360dd_cmd <= 1'd0;
ibm360dd_length <= 1'd0;
ibm360dd_address <= 1'd0;
ibm360dd_data <= 1'd0;
ibm360dd_count <= 23'd5000000;
io_storage_full <= 9'd511;
io_re <= 1'd0;
user_led_2 <= 1'd0;
sigs_counter <= 1'd0;
sigs_index_edge <= 1'd0;
sigs_latched_index <= 1'd0;
sigs_dat_counter <= 1'd0;
user_led_3 <= 1'd0;
sigs_data_edge <= 1'd0;
sigs_latched_data <= 1'd0;
frontend_buffer_source_payload_data <= 1'd0;
frontend_buffer_source_payload_hit <= 1'd0;
frontend_buffer_valid_n <= 1'd0;
frontend_buffer_last_n <= 1'd0;
frontend_trigger_value_storage_full <= 1'd0;
frontend_trigger_value_re <= 1'd0;
frontend_trigger_mask_storage_full <= 1'd0;
frontend_trigger_mask_re <= 1'd0;
frontend_subsampler_value_storage_full <= 1'd0;
frontend_subsampler_value_re <= 1'd0;
frontend_subsampler_counter <= 1'd0;
frontend_asyncfifo_graycounter0_q <= 1'd0;
frontend_asyncfifo_graycounter0_q_binary <= 1'd0;
frontend_asyncfifo_graycounter1_q <= 1'd0;
frontend_asyncfifo_graycounter1_q_binary <= 1'd0;
storage_length_storage_full <= 1'd0;
storage_length_re <= 1'd0;
storage_offset_storage_full <= 1'd0;
storage_offset_re <= 1'd0;
storage_mem_readable <= 1'd0;
storage_mem_level0 <= 1'd0;
storage_mem_produce <= 1'd0;
storage_mem_consume <= 1'd0;
uartwishbonebridge_state <= 1'd0;
litescopeanalyzer_state <= 1'd0;
slave_sel_r <= 1'd0;
interface0_dat_r <= 1'd0;
mmap_sel_r <= 1'd0;
interface2_dat_r <= 1'd0;
end else begin
sigs_latched_index <= INDEX;
sigs_index_edge <= (sigs_latched_index & (~INDEX));
if (sigs_index_edge) begin
sigs_index_edge <= 1'd0;
sigs_counter <= (sigs_counter + 1'd1);
end
if ((sigs_counter >= 3'd5)) begin
sigs_counter <= 1'd0;
user_led_2 <= (~user_led_2);
end
sigs_latched_data <= RDATA;
sigs_data_edge <= (sigs_latched_data ^ RDATA);
if (sigs_data_edge) begin
sigs_data_edge <= 1'd0;
sigs_dat_counter <= (sigs_dat_counter + 1'd1);
end
if ((sigs_dat_counter >= 19'd500000)) begin
sigs_dat_counter <= 1'd0;
user_led_3 <= (~user_led_3);
end
ibm360dd_sram_bus_ack <= 1'd0;
if (((ibm360dd_sram_bus_cyc & ibm360dd_sram_bus_stb) & (~ibm360dd_sram_bus_ack))) begin
ibm360dd_sram_bus_ack <= 1'd1;
end
ibm360dd_interface_we <= 1'd0;
ibm360dd_interface_dat_w <= ibm360dd_bus_wishbone_dat_w;
ibm360dd_interface_adr <= ibm360dd_bus_wishbone_adr;
ibm360dd_bus_wishbone_dat_r <= ibm360dd_interface_dat_r;
if ((ibm360dd_counter == 1'd1)) begin
ibm360dd_interface_we <= ibm360dd_bus_wishbone_we;
end
if ((ibm360dd_counter == 2'd2)) begin
ibm360dd_bus_wishbone_ack <= 1'd1;
end
if ((ibm360dd_counter == 2'd3)) begin
ibm360dd_bus_wishbone_ack <= 1'd0;
end
if ((ibm360dd_counter != 1'd0)) begin
ibm360dd_counter <= (ibm360dd_counter + 1'd1);
end else begin
if ((ibm360dd_bus_wishbone_cyc & ibm360dd_bus_wishbone_stb)) begin
ibm360dd_counter <= 1'd1;
end
end
if (ibm360dd_byte_counter_reset) begin
ibm360dd_byte_counter <= 1'd0;
end else begin
if (ibm360dd_byte_counter_ce) begin
ibm360dd_byte_counter <= (ibm360dd_byte_counter + 1'd1);
end
end
if (ibm360dd_word_counter_reset) begin
ibm360dd_word_counter <= 1'd0;
end else begin
if (ibm360dd_word_counter_ce) begin
ibm360dd_word_counter <= (ibm360dd_word_counter + 1'd1);
end
end
if (ibm360dd_cmd_ce) begin
ibm360dd_cmd <= ibm360dd_source_payload_data;
end
if (ibm360dd_length_ce) begin
ibm360dd_length <= ibm360dd_source_payload_data;
end
if (ibm360dd_address_ce) begin
ibm360dd_address <= {ibm360dd_address[23:0], ibm360dd_source_payload_data};
end
if (ibm360dd_rx_data_ce) begin
ibm360dd_data <= {ibm360dd_data[23:0], ibm360dd_source_payload_data};
end else begin
if (ibm360dd_tx_data_ce) begin
ibm360dd_data <= ibm360dd_wishbone_dat_r;
end
end
ibm360dd_sink_ready <= 1'd0;
if (((ibm360dd_sink_valid & (~ibm360dd_tx_busy)) & (~ibm360dd_sink_ready))) begin
ibm360dd_tx_reg <= ibm360dd_sink_payload_data;
ibm360dd_tx_bitcount <= 1'd0;
ibm360dd_tx_busy <= 1'd1;
serial_tx <= 1'd0;
end else begin
if ((ibm360dd_uart_clk_txen & ibm360dd_tx_busy)) begin
ibm360dd_tx_bitcount <= (ibm360dd_tx_bitcount + 1'd1);
if ((ibm360dd_tx_bitcount == 4'd8)) begin
serial_tx <= 1'd1;
end else begin
if ((ibm360dd_tx_bitcount == 4'd9)) begin
serial_tx <= 1'd1;
ibm360dd_tx_busy <= 1'd0;
ibm360dd_sink_ready <= 1'd1;
end else begin
serial_tx <= ibm360dd_tx_reg[0];
ibm360dd_tx_reg <= {1'd0, ibm360dd_tx_reg[7:1]};
end
end
end
end
if (ibm360dd_tx_busy) begin
{ibm360dd_uart_clk_txen, ibm360dd_phase_accumulator_tx} <= (ibm360dd_phase_accumulator_tx + ibm360dd_storage);
end else begin
{ibm360dd_uart_clk_txen, ibm360dd_phase_accumulator_tx} <= 1'd0;
end
ibm360dd_source_valid <= 1'd0;
ibm360dd_rx_r <= ibm360dd_rx;
if ((~ibm360dd_rx_busy)) begin
if (((~ibm360dd_rx) & ibm360dd_rx_r)) begin
ibm360dd_rx_busy <= 1'd1;
ibm360dd_rx_bitcount <= 1'd0;
end
end else begin
if (ibm360dd_uart_clk_rxen) begin
ibm360dd_rx_bitcount <= (ibm360dd_rx_bitcount + 1'd1);
if ((ibm360dd_rx_bitcount == 1'd0)) begin
if (ibm360dd_rx) begin
ibm360dd_rx_busy <= 1'd0;
end
end else begin
if ((ibm360dd_rx_bitcount == 4'd9)) begin
ibm360dd_rx_busy <= 1'd0;
if (ibm360dd_rx) begin
ibm360dd_source_payload_data <= ibm360dd_rx_reg;
ibm360dd_source_valid <= 1'd1;
end
end else begin
ibm360dd_rx_reg <= {ibm360dd_rx, ibm360dd_rx_reg[7:1]};
end
end
end
end
if (ibm360dd_rx_busy) begin
{ibm360dd_uart_clk_rxen, ibm360dd_phase_accumulator_rx} <= (ibm360dd_phase_accumulator_rx + ibm360dd_storage);
end else begin
{ibm360dd_uart_clk_rxen, ibm360dd_phase_accumulator_rx} <= 32'd2147483648;
end
if (ibm360dd_reset) begin
uartwishbonebridge_state <= 1'd0;
end else begin
uartwishbonebridge_state <= uartwishbonebridge_next_state;
end
if (ibm360dd_wait) begin
if ((~ibm360dd_done)) begin
ibm360dd_count <= (ibm360dd_count - 1'd1);
end
end else begin
ibm360dd_count <= 23'd5000000;
end
if (frontend_buffer_pipe_ce) begin
frontend_buffer_valid_n <= frontend_buffer_sink_valid;
end
if (frontend_buffer_pipe_ce) begin
frontend_buffer_last_n <= (frontend_buffer_sink_valid & frontend_buffer_sink_last);
end
if (frontend_buffer_pipe_ce) begin
frontend_buffer_source_payload_data <= frontend_buffer_sink_payload_data;
frontend_buffer_source_payload_hit <= frontend_buffer_sink_payload_hit;
end
if (frontend_subsampler_source_ready) begin
if (frontend_subsampler_done) begin
frontend_subsampler_counter <= 1'd0;
end else begin
if (frontend_subsampler_sink_valid) begin
frontend_subsampler_counter <= (frontend_subsampler_counter + 1'd1);
end
end
end
frontend_asyncfifo_graycounter0_q_binary <= frontend_asyncfifo_graycounter0_q_next_binary;
frontend_asyncfifo_graycounter0_q <= frontend_asyncfifo_graycounter0_q_next;
frontend_asyncfifo_graycounter1_q_binary <= frontend_asyncfifo_graycounter1_q_next_binary;
frontend_asyncfifo_graycounter1_q <= frontend_asyncfifo_graycounter1_q_next;
if (storage_mem_syncfifo_re) begin
storage_mem_readable <= 1'd1;
end else begin
if (storage_mem_re) begin
storage_mem_readable <= 1'd0;
end
end
if (((storage_mem_syncfifo_we & storage_mem_syncfifo_writable) & (~storage_mem_replace))) begin
storage_mem_produce <= (storage_mem_produce + 1'd1);
end
if (storage_mem_do_read) begin
storage_mem_consume <= (storage_mem_consume + 1'd1);
end
if (((storage_mem_syncfifo_we & storage_mem_syncfifo_writable) & (~storage_mem_replace))) begin
if ((~storage_mem_do_read)) begin
storage_mem_level0 <= (storage_mem_level0 + 1'd1);
end
end else begin
if (storage_mem_do_read) begin
storage_mem_level0 <= (storage_mem_level0 - 1'd1);
end
end
litescopeanalyzer_state <= litescopeanalyzer_next_state;
slave_sel_r <= slave_sel;
interface0_dat_r <= 1'd0;
if (csrbank0_sel) begin
case (interface0_adr[3:0])
1'd0: begin
interface0_dat_r <= csrbank0_frontend_trigger_value0_w;
end
1'd1: begin
interface0_dat_r <= csrbank0_frontend_trigger_mask0_w;
end
2'd2: begin
interface0_dat_r <= csrbank0_frontend_subsampler_value0_w;
end
2'd3: begin
interface0_dat_r <= storage_start_w;
end
3'd4: begin
interface0_dat_r <= csrbank0_storage_length0_w;
end
3'd5: begin
interface0_dat_r <= csrbank0_storage_offset0_w;
end
3'd6: begin
interface0_dat_r <= csrbank0_storage_idle_w;
end
3'd7: begin
interface0_dat_r <= csrbank0_storage_wait_w;
end
4'd8: begin
interface0_dat_r <= csrbank0_storage_run_w;
end
4'd9: begin
interface0_dat_r <= csrbank0_storage_mem_valid_w;
end
4'd10: begin
interface0_dat_r <= storage_mem_ready_w;
end
4'd11: begin
interface0_dat_r <= csrbank0_storage_mem_data_w;
end
endcase
end
if (csrbank0_frontend_trigger_value0_re) begin
frontend_trigger_value_storage_full[1:0] <= csrbank0_frontend_trigger_value0_r;
end
frontend_trigger_value_re <= csrbank0_frontend_trigger_value0_re;
if (csrbank0_frontend_trigger_mask0_re) begin
frontend_trigger_mask_storage_full[1:0] <= csrbank0_frontend_trigger_mask0_r;
end
frontend_trigger_mask_re <= csrbank0_frontend_trigger_mask0_re;
if (csrbank0_frontend_subsampler_value0_re) begin
frontend_subsampler_value_storage_full[15:0] <= csrbank0_frontend_subsampler_value0_r;
end
frontend_subsampler_value_re <= csrbank0_frontend_subsampler_value0_re;
if (csrbank0_storage_length0_re) begin
storage_length_storage_full[14:0] <= csrbank0_storage_length0_r;
end
storage_length_re <= csrbank0_storage_length0_re;
if (csrbank0_storage_offset0_re) begin
storage_offset_storage_full[14:0] <= csrbank0_storage_offset0_r;
end
storage_offset_re <= csrbank0_storage_offset0_re;
mmap_sel_r <= mmap_sel;
interface2_dat_r <= 1'd0;
if (csrbank1_sel) begin
case (interface2_adr[0])
1'd0: begin
interface2_dat_r <= csrbank1_input_w;
end
1'd1: begin
interface2_dat_r <= csrbank1_output0_w;
end
endcase
end
if (csrbank1_output0_re) begin
io_storage_full[8:0] <= csrbank1_output0_r;
end
io_re <= csrbank1_output0_re;
end
xilinxmultiregvivadoimpl0_regs0 <= serial_rx;
xilinxmultiregvivadoimpl0_regs1 <= xilinxmultiregvivadoimpl0_regs0;
xilinxmultiregvivadoimpl1_regs0 <= frontend_trigger_value_storage;
xilinxmultiregvivadoimpl1_regs1 <= xilinxmultiregvivadoimpl1_regs0;
xilinxmultiregvivadoimpl2_regs0 <= frontend_trigger_mask_storage;
xilinxmultiregvivadoimpl2_regs1 <= xilinxmultiregvivadoimpl2_regs0;
xilinxmultiregvivadoimpl3_regs0 <= frontend_subsampler_value_storage;
xilinxmultiregvivadoimpl3_regs1 <= xilinxmultiregvivadoimpl3_regs0;
xilinxmultiregvivadoimpl4_regs0 <= frontend_asyncfifo_graycounter0_q;
xilinxmultiregvivadoimpl4_regs1 <= xilinxmultiregvivadoimpl4_regs0;
xilinxmultiregvivadoimpl5_regs0 <= frontend_asyncfifo_graycounter1_q;
xilinxmultiregvivadoimpl5_regs1 <= xilinxmultiregvivadoimpl5_regs0;
end
reg [31:0] mem[0:1023];
reg [9:0] memadr;
always @(posedge sys_clk) begin
if (ibm360dd_sram_we[0])
mem[ibm360dd_sram_adr][7:0] <= ibm360dd_sram_dat_w[7:0];
if (ibm360dd_sram_we[1])
mem[ibm360dd_sram_adr][15:8] <= ibm360dd_sram_dat_w[15:8];
if (ibm360dd_sram_we[2])
mem[ibm360dd_sram_adr][23:16] <= ibm360dd_sram_dat_w[23:16];
if (ibm360dd_sram_we[3])
mem[ibm360dd_sram_adr][31:24] <= ibm360dd_sram_dat_w[31:24];
memadr <= ibm360dd_sram_adr;
end
assign ibm360dd_sram_dat_r = mem[memadr];
reg [7:0] mem_1[0:16];
reg [7:0] memdat;
always @(posedge sys_clk) begin
memdat <= mem_1[mmap_adr];
end
assign mmap_dat_r = memdat;
initial begin
//$readmemh("mem_1.init", mem_1);
end
reg [3:0] storage[0:7];
reg [2:0] memadr_1;
reg [3:0] memdat_1;
always @(posedge sys_clk) begin
if (frontend_asyncfifo_wrport_we)
storage[frontend_asyncfifo_wrport_adr] <= frontend_asyncfifo_wrport_dat_w;
memadr_1 <= frontend_asyncfifo_wrport_adr;
end
always @(posedge sys_clk) begin
memdat_1 <= storage[frontend_asyncfifo_rdport_adr];
end
assign frontend_asyncfifo_wrport_dat_r = storage[memadr_1];
assign frontend_asyncfifo_rdport_dat_r = memdat_1;
reg [2:0] storage_1[0:16383];
reg [13:0] memadr_2;
reg [2:0] memdat_2;
always @(posedge sys_clk) begin
if (storage_mem_wrport_we)
storage_1[storage_mem_wrport_adr] <= storage_mem_wrport_dat_w;
memadr_2 <= storage_mem_wrport_adr;
end
always @(posedge sys_clk) begin
if (storage_mem_rdport_re)
memdat_2 <= storage_1[storage_mem_rdport_adr];
end
assign storage_mem_wrport_dat_r = storage_1[memadr_2];
assign storage_mem_rdport_dat_r = memdat_2;
endmodule
regression/issue_00183/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
//$dumpfile("testbench.vcd");
//$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire out;
top uut (clk,out);
assert_dff check_output (clk,out,1'b1);
endmodule
regression/issue_00183/top.v 0 → 100644
module top(input in,output out);
SB_DFF dff(out,in,1);
endmodule
regression/issue_00186/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
//$dumpfile("testbench.vcd");
//$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] adr = 0;
reg [1:0] din = 0;
wire [1:0] q;
reg mem_init = 0;
always @(posedge clk) begin
#3;
din <= din + 1;
adr <= adr + 1;
end
always @(posedge adr) begin
#10;
if(adr == 2'b11)
mem_init <= 1;
end
top uut (adr,clk,din,q);
uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .A(q));
endmodule
module uut_mem_checker(input clk, input init, input [1:0] A);
always @(posedge clk)
begin
#1;
if (init == 1 & A === 2'bXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00186/top.v 0 → 100644
`define TEST_1
module top (
input [1:0] adr,
input clk,
input [1:0] din,
output reg [1:0] q
);
reg [1:0] ram [3:0];
always@(posedge clk)
begin
`ifdef TEST_1
{ram[adr],q} <= {din, ram[adr]};
`elsif TEST_2
ram[adr] <= din;
q <= ram[adr];
`endif
end
endmodule
regression/issue_00194/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
//$dumpfile("testbench.vcd");
//$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire out;
top uut (clk,out);
assert_dff check_output (clk,out,1'b1);
endmodule
regression/issue_00194/top.v 0 → 100644
module top(input a, output y);
demo_sub sub (y, , 1'b1, a);
endmodule
module demo_sub(output y, z, input a, b);
assign y = a & b, z = a | b;
endmodule
regression/issue_00195/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00195/top.v 0 → 100644
module top(b);
input b;
wire a = 100_000.0;
endmodule
regression/issue_00196/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire a,b,c,d,e,f;
top uut(clk,a,b,c,d,e,f);
endmodule
regression/issue_00196/top.v 0 → 100644
module top(p1h, p1l, p2h, p2l, p3h, p3l);
(* LOC="P3" *) output p1h;
(* LOC="P4" *) output p1l;
(* LOC="P5" *) output p2h;
(* LOC="P6" *) output p2l;
(* LOC="P7" *) output p3h;
(* LOC="P8" *) output p3l;
wire clk;
GP_LFOSC #(
.AUTO_PWRDN(0),
.OUT_DIV(1)
) osc (
.CLKOUT(clk)
);
localparam DIVIDER = 1;//400;
reg [13:0] divcnt = DIVIDER;
always @(posedge clk)
if(divcnt == 0)
divcnt <= DIVIDER;
else
divcnt <= divcnt - 1;
wire reset;
GP_POR por(
.RST_DONE(reset)
);
reg [2:0] state;
always @(posedge divcnt or negedge reset)
if(!reset)
state <= 0;
else
case(state)
0: state <= 1;
1: state <= 2;
2: state <= 3;
3: state <= 4;
4: state <= 5;
5: state <= 0;
endcase
reg [5:0] phases;
always @(*) begin
phases <= 6'b000000;
case(state)
0: phases <= 6'b100100;
1: phases <= 6'b000110;
2: phases <= 6'b010010;
3: phases <= 6'b011000;
4: phases <= 6'b001001;
5: phases <= 6'b100001;
endcase
end
wire p1i, p2i, p3i;
assign {p1i, p1l, p2i, p2l, p3i, p3l} = phases;
assign {p1h, p2h, p3h} = ~{p1i, p2i, p3i};
endmodule
regression/issue_00210/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [9:0] a;
top uut(a);
endmodule
regression/issue_00210/top.v 0 → 100644
module top(result);
output signed [9:0] result;
wire signed [9:0] intermediate [0:2];
function integer depth2Index;
input integer depth;
depth2Index = depth;
endfunction
assign intermediate[depth2Index(2)] = 0;
assign result = intermediate[2];
endmodule
regression/issue_00253/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [3:0] in = 2;
reg [1:0] count = 0;
reg init = 0;
wire [7:0] out;
always @(posedge clk)
begin
in = in + 7;
count = count + 1;
if (count == 2'b11)
init = 1;
end
top uut(clk,in,out);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
check_X check_output(clk,init,out[index]);
end
endgenerate
endmodule
module check_X(input clk,input init, input A);
always @(posedge clk)
begin
#1;
if (A === 1'bX && init == 1'b1)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00253/top.v 0 → 100644
module top(input clk,input[3:0] in, output [7:0] out);
reg[2:0] state;
always @(posedge clk) begin
out<=0;
case (state)
0: begin
if(in == 0) begin
state<=1;
out<=0;
end
if(in == 1) begin
state<=2;
out<=1;
end
if(in == 2) begin
state<=5;
out<=2;
end
end
1: begin
if(in == 0) begin
state<=1;
out<=3;
end
if(in == 1) begin
state<=3;
out<=4;
end
if(in == 2) begin
state<=1;
out<=5;
end
if(in == 3) begin
state<=3;
out<=6;
end
if(in == 4) begin
state<=2;
out<=7;
end
if(in == 5) begin
state<=5;
out<=8;
end
if(in == 6) begin
state<=3;
out<=9;
end
if(in == 7) begin
state<=5;
out<=10;
end
if(in == 8) begin
state<=3;
out<=11;
end
if(in == 9) begin
state<=2;
out<=12;
end
end
2: begin
if(in == 0) begin
state<=2;
out<=13;
end
if(in == 1) begin
state<=2;
out<=14;
end
if(in == 2) begin
state<=1;
out<=15;
end
if(in == 3) begin
state<=1;
out<=16;
end
if(in == 4) begin
state<=2;
out<=17;
end
if(in == 5) begin
state<=2;
out<=18;
end
if(in == 6) begin
state<=2;
out<=19;
end
if(in == 7) begin
state<=5;
out<=20;
end
if(in == 8) begin
state<=5;
out<=21;
end
if(in == 9) begin
state<=2;
out<=22;
end
end
3: begin
if(in == 0) begin
state<=3;
out<=23;
end
if(in == 1) begin
state<=3;
out<=24;
end
if(in == 2) begin
state<=3;
out<=25;
end
if(in == 3) begin
state<=3;
out<=26;
end
if(in == 4) begin
state<=4;
out<=27;
end
if(in == 5) begin
state<=5;
out<=28;
end
if(in == 6) begin
state<=3;
out<=29;
end
if(in == 7) begin
state<=5;
out<=30;
end
if(in == 8) begin
state<=3;
out<=31;
end
if(in == 9) begin
state<=2;
out<=32;
end
end
4: begin
if(in == 0) begin
state<=4;
out<=33;
end
if(in == 1) begin
state<=4;
out<=34;
end
if(in == 2) begin
state<=3;
out<=35;
end
if(in == 3) begin
state<=3;
out<=36;
end
if(in == 4) begin
state<=4;
out<=37;
end
if(in == 5) begin
state<=2;
out<=38;
end
if(in == 6) begin
state<=2;
out<=39;
end
if(in == 7) begin
state<=5;
out<=40;
end
if(in == 8) begin
state<=5;
out<=41;
end
if(in == 9) begin
state<=2;
out<=42;
end
end
5: begin
if(in == 0) begin
state<=1;
out<=43;
end
if(in == 1) begin
state<=1;
out<=44;
end
if(in == 2) begin
state<=1;
out<=45;
end
if(in == 3) begin
state<=1;
out<=46;
end
if(in == 4) begin
state<=2;
out<=47;
end
if(in == 5) begin
state<=5;
out<=48;
end
if(in == 6) begin
state<=5;
out<=49;
end
if(in == 7) begin
state<=5;
out<=50;
end
if(in == 8) begin
state<=5;
out<=51;
end
if(in == 9) begin
state<=2;
out<=52;
end
end
endcase
end
endmodule
regression/issue_00282/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [3:0] in = 2;
reg [1:0] count = 0;
reg init = 0;
wire [7:0] out;
always @(posedge clk)
begin
in = in + 7;
count = count + 1;
if (count == 2'b11)
init = 1;
end
top uut(clk,in,out);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
check_X check_output(clk,init,out[index]);
end
endgenerate
endmodule
module check_X(input clk,input init, input A);
always @(posedge clk)
begin
#1;
if (A === 1'bX && init == 1'b1)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00282/top.v 0 → 100644
module top(input clk,input[3:0] in, output [7:0] out);
reg[2:0] state;
always @(posedge clk) begin
out<=0;
case (state)
0: begin
if(in == 0) begin
state<=1;
out<=0;
end
if(in == 1) begin
state<=2;
out<=1;
end
if(in == 2) begin
state<=5;
out<=2;
end
end
1: begin
if(in == 0) begin
state<=1;
out<=3;
end
if(in == 1) begin
state<=3;
out<=4;
end
if(in == 2) begin
state<=1;
out<=5;
end
if(in == 3) begin
state<=3;
out<=6;
end
if(in == 4) begin
state<=2;
out<=7;
end
if(in == 5) begin
state<=5;
out<=8;
end
if(in == 6) begin
state<=3;
out<=9;
end
if(in == 7) begin
state<=5;
out<=10;
end
if(in == 8) begin
state<=3;
out<=11;
end
if(in == 9) begin
state<=2;
out<=12;
end
end
2: begin
if(in == 0) begin
state<=2;
out<=13;
end
if(in == 1) begin
state<=2;
out<=14;
end
if(in == 2) begin
state<=1;
out<=15;
end
if(in == 3) begin
state<=1;
out<=16;
end
if(in == 4) begin
state<=2;
out<=17;
end
if(in == 5) begin
state<=2;
out<=18;
end
if(in == 6) begin
state<=2;
out<=19;
end
if(in == 7) begin
state<=5;
out<=20;
end
if(in == 8) begin
state<=5;
out<=21;
end
if(in == 9) begin
state<=2;
out<=22;
end
end
3: begin
if(in == 0) begin
state<=3;
out<=23;
end
if(in == 1) begin
state<=3;
out<=24;
end
if(in == 2) begin
state<=3;
out<=25;
end
if(in == 3) begin
state<=3;
out<=26;
end
if(in == 4) begin
state<=4;
out<=27;
end
if(in == 5) begin
state<=5;
out<=28;
end
if(in == 6) begin
state<=3;
out<=29;
end
if(in == 7) begin
state<=5;
out<=30;
end
if(in == 8) begin
state<=3;
out<=31;
end
if(in == 9) begin
state<=2;
out<=32;
end
end
4: begin
if(in == 0) begin
state<=4;
out<=33;
end
if(in == 1) begin
state<=4;
out<=34;
end
if(in == 2) begin
state<=3;
out<=35;
end
if(in == 3) begin
state<=3;
out<=36;
end
if(in == 4) begin
state<=4;
out<=37;
end
if(in == 5) begin
state<=2;
out<=38;
end
if(in == 6) begin
state<=2;
out<=39;
end
if(in == 7) begin
state<=5;
out<=40;
end
if(in == 8) begin
state<=5;
out<=41;
end
if(in == 9) begin
state<=2;
out<=42;
end
end
5: begin
if(in == 0) begin
state<=1;
out<=43;
end
if(in == 1) begin
state<=1;
out<=44;
end
if(in == 2) begin
state<=1;
out<=45;
end
if(in == 3) begin
state<=1;
out<=46;
end
if(in == 4) begin
state<=2;
out<=47;
end
if(in == 5) begin
state<=5;
out<=48;
end
if(in == 6) begin
state<=5;
out<=49;
end
if(in == 7) begin
state<=5;
out<=50;
end
if(in == 8) begin
state<=5;
out<=51;
end
if(in == 9) begin
state<=2;
out<=52;
end
end
endcase
end
endmodule
regression/issue_00283/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire y;
top uut(clk,1'b1,y);
assert_X check_output(clk,y);
endmodule
regression/issue_00283/top.v 0 → 100644
module top(input clk, enable, output reg y);
wire [1:0] foo [1:0];
integer i;
initial begin
for (i=0;i<=1;i=i+1)
foo[i] = 2'b11;
end
always @(posedge clk)
if (enable)
for (i = 0; i < 2; i=i+1)
y <= foo[0][0];
endmodule
regression/issue_00287/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [6:0] D = 0;
reg [1:0] S = 0;
wire [1:0] Y;
reg [1:0] Y_p;
always @(posedge clk)
begin
D = D + 3;
S = S + 1;
end
always @* begin : block
reg [3:0] data [0:3];
data[0] = D[3:0];
data[1] = D[4:1];
data[2] = D[5:2];
data[3] = D[6:3];
Y_p = data[S];
end
top uut(D,S,Y);
assert_dff check_Y0 (clk,Y[0],Y_p[0]);
assert_dff check_Y1 (clk,Y[1],Y_p[1]);
endmodule
regression/issue_00287/top.v 0 → 100644
module top(input [6:0] D, input [1:0] S, output reg [1:0] Y);
always @* begin : block
reg [3:0] data [0:3];
data[0] = D[3:0];
data[1] = D[4:1];
data[2] = D[5:2];
data[3] = D[6:3];
Y = data[S];
end
endmodule
regression/issue_00289/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire o;
top uut(clk,o);
assert_dff check_o (clk,clk,o);
endmodule
regression/issue_00289/top.v 0 → 100644
function f(input i);
reg [1:0] mem0 [1:0];
f = i;
endfunction
module top(in,out);
input in;
output out;
assign out = f(in);
endmodule
regression/issue_00291/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg rst = 0;
reg any_pop = 0;
reg any_push = 0;
always @(posedge clk)
begin
rst = 1;
#1
any_pop = ~any_pop;
#3
any_push = ~any_push;
end
top uut(rst,clk,any_push,any_pop);
endmodule
regression/issue_00291/top.v 0 → 100644
module top (
input reset,
input clk,
input any_push,
input any_pop
);
reg [1:0] fifo_head [3:0];
reg [1:0] fifo_next [3:0];
wire [1:0] fifo_head4samp [3:0];
genvar fifo_num ;
integer pntr_num,fifoifo_num;
generate
for (fifo_num=0; fifo_num<4; fifo_num=fifo_num+1) begin:fifo_gen
assign fifo_head4samp[fifo_num] = fifo_next[fifo_head[fifo_num]] ; /* this is line 16 */
end
endgenerate
always @(posedge clk or negedge reset)
begin
if (!reset) begin
for (pntr_num=0; pntr_num<4; pntr_num=pntr_num+1)
fifo_next[pntr_num] <= {2{1'b0}} ;
end
else if (any_push | any_pop) begin
for (fifoifo_num=0; fifoifo_num<4; fifoifo_num=fifoifo_num+1) begin
fifo_head[fifoifo_num] <= fifo_head4samp[fifoifo_num] ;
end
end
end
endmodule
regression/issue_00300/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] addr = 0;
reg [7:0] wdata = 0;
wire [7:0] rdata;
wire [7:0] rdata_o;
always @(posedge clk)
begin
addr = addr + 1;
wdata = wdata + 17;
end
reg [7:0] memory [255:0];
assign rdata = memory[addr];
always @(posedge clk) memory[addr] <= wdata;
top uut(clk,addr,wdata,rdata_o);
uut_mem_checker port_b_test(.clk(clk), .A(rdata), .B(rdata_o));
endmodule
module uut_mem_checker(input clk, input [7:0] A, input [7:0] B);
always @(posedge clk)
begin
#1;
if (A == B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/issue_00300/top.v 0 → 100644
module top(input clk, input [7:0] addr, wdata, output [7:0] rdata);
reg [7:0] memory [255:0];
assign rdata = memory[addr];
always @(posedge clk) memory[addr] <= wdata;
endmodule
regression/issue_00306/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [3:0] a = 0;
wire res_p;
wire res;
always @(posedge clk)
begin
a = a + 1;
end
assign res_p = a < 6'b100000;
top uut(a,res);
assert_dff check_res (clk,res, res_p);
endmodule
regression/issue_00306/top.v 0 → 100644
module top (input [3:0] a, output res);
assign res = a < 6'b100000;
endmodule
regression/issue_00314/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
reg [7:0] b = 0;
wire [7:0] z;
always @(posedge clk)
begin
a = a + 1;
b = b + 7;
end
top uut(a,b,z);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
assert_Z check_output(clk,z[index]);
end
endgenerate
endmodule
regression/issue_00314/top.v 0 → 100644
module top(a,b,z);
parameter width_a = 8;
parameter width_b = 8;
input [width_a-1:0] a;
input [width_b-1:0] b;
output [width_a-1:0] z;
reg [width_a-1:0] z;
always@(a or b)
begin
div_u(a,b,z);
end
function [width_b:0] minus;
input [width_b:0] in1;
input [width_b:0] in2;
minus = in1 - in2;
endfunction
task divmod;
input [width_a-1:0] l;
input [width_b-1:0] r;
output [width_a-1:0] rdiv;
output [width_b-1:0] rmod;
parameter llen = width_a;
parameter rlen = width_b;
reg [(llen+rlen)-1:0] lbuf;
reg [rlen:0] diff;
integer i;
begin
lbuf = 0;
lbuf[llen-1:0] = l;
for(i=width_a-1;i>=0;i=i-1)
begin
diff = minus(lbuf[(llen+rlen)-1:llen-1], {1'b0,r});
rdiv[i] = ~diff[rlen];
if(diff[rlen] == 0)
lbuf[(llen+rlen)-1:llen-1] = diff;
lbuf[(llen+rlen)-1:1] = lbuf[(llen+rlen)-2:0];
end
rmod = lbuf[(llen+rlen)-1:llen];
end
endtask
task div_u;
input [width_a-1:0] l;
input [width_b-1:0] r;
output [width_a-1:0] rdiv;
reg [width_a-01:0] rdiv; // <-- this line causes problem
reg [width_b-1:0] rmod;
begin
divmod(l, r, rdiv, rmod);
end
endtask
endmodule
regression/issue_00317/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] in = 0;
wire [7:0] out;
always @(posedge clk) begin
in <= in + 1;
end
top uut (
.alu_data_d_in (in ),
.alu_data_d_out (out )
);
uut_checker q_test(.clk(clk), .A(out));
endmodule
module uut_checker(input clk, input [7:0] A);
always @(posedge clk)
begin
#1;
if (A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00317/top.v 0 → 100644
module top(
alu_data_d_in,
alu_data_d_out
);
input [7:0]alu_data_d_in;
output[7:0]alu_data_d_out;
wire [7:0]swap_out;
genvar i;
generate
for ( i = 7 ; ( i >= 4 ) ; i-- )
begin : swap_h
assign swap_out[i] = alu_data_d_in[( ( i - 4 ) )];
end
endgenerate
generate
for ( i = 0 ; ( i <4 ) ; i++ )
begin : swap_l
assign swap_out[i] = alu_data_d_in[(i+4 )];
end
endgenerate
assign alu_data_d_out = swap_out;
endmodule
regression/issue_00341/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i1,i2 = 0;
wire o1g,o2g;
wire o1r,o2r;
wire o1w,o2w;
wire o1gt,o2gt;
wire o1rt,o2rt;
wire o1wt,o2wt;
always @(posedge clk) begin
i1 <= i1 + 1;
i2 <= i2 + 1;
end
gold uut_g (
i1,i2,o1g,o2g
);
top_r uut_r (
i1,i2,o1r,o2r
);
top_w uut_w (
i1,i2,o1w,o2w
);
goldt uut_gt (
i1,i2,o1gt,o2gt
);
top_rt uut_rt (
i1,i2,o1rt,o2rt
);
top_wt uut_wt (
i1,i2,o1wt,o2wt
);
assert_dff gold_test(clk,o1g,o1gt);
assert_dff top_r_test(clk,o1r,o1rt);
assert_dff top_w_test(clk,o1w,o1wt);
endmodule
module goldt(input i1, input i2, output o2, output o1);
wire _1_;
assign o2 = i1 & i2;
assign _1_ = i1 | i2;
assign o1 = _1_ & o2;
endmodule
module top_rt( i1, i2, o1, o2 );
input i1, i2;
output o1, o2;
wire w4;
assign o2 = (i2 & i1);
assign w4 = ((i2 && i1) | (i2) | (i1));
assign o1 = ((w4 & o2));
endmodule
module top_wt( i1, i2, o1, o2 );
input i1, i2;
output o1, o2;
wire w4;
assign o2 = (i2 & i1);
assign w4 = ((i2 & i1) | (i2) | (i1));
assign o1 = ((w4 & o2));
endmodule
regression/issue_00341/top.v 0 → 100644
module gold(input i1, input i2, output o2, output o1);
wire _1_;
assign o2 = i1 & i2;
assign _1_ = i1 | i2;
assign o1 = _1_ & o2;
endmodule
module top_r( i1, i2, o1, o2 );
input i1, i2;
output o1, o2;
wire w4;
assign o2 = (i2 & i1);
assign w4 = ((i2 && i1) | (i2) | (i1));
assign o1 = ((w4 & o2));
endmodule
module top_w( i1, i2, o1, o2 );
input i1, i2;
output o1, o2;
wire w4;
assign o2 = (i2 & i1);
assign w4 = ((i2 & i1) | (i2) | (i1));
assign o1 = ((w4 & o2));
endmodule
regression/issue_00342/testbench.v 0 → 100644
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] addr = 0;
reg [7:0] wdata = 0;
wire [7:0] rdata;
wire [7:0] rdata_o;
always @(posedge clk)
begin
addr = addr + 1;
wdata = wdata + 17;
end
logic [8-1:0] mem [8-1:0];
assign rdata_o = mem[addr];
always @*
if (clk)
mem[addr] <= wdata;
top uut(rdata,wdata,addr,clk,clk);
uut_mem_checker port_b_test(.clk(clk), .A(rdata), .B(rdata_o));
endmodule
module uut_mem_checker(input clk, input [7:0] A, input [7:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/issue_00342/top.v 0 → 100644
`timescale 1ns / 1ns
module top #(parameter AWIDTH=8,
localparam DEPTH=1<<AWIDTH,
parameter DWIDTH=8)
(output [DWIDTH-1:0] rdata,
input [DWIDTH-1:0] wdata,
input [AWIDTH-1:0] addr,
input r_wn, cs_n);
logic [DWIDTH-1:0] mem [DEPTH];
assign rdata = mem[addr];
always_latch
if (!cs_n && !r_wn) mem[addr] <= wdata;
endmodule
regression/issue_00349/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] in = 0;
reg z_p;
wire z;
always @(posedge clk) begin
in <= in + 1;
end
always @*
z_p <= in[0] ~& in[1];
top uut (in[0],in[1],z);
assert_dff z_test(clk,z,z_p);
endmodule
regression/issue_00349/top.v 0 → 100644
module top (input wire x, input wire y, output reg z);
always @*
z <= x ~& y;
endmodule
regression/issue_00350/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i;
wire o_p;
wire o;
always @(posedge clk) begin
#2
i <= ~i;
end
reg q = 0;
always @(posedge clk) q <= 1;
assign o_p = q & i;
top uut (clk,i,o);
assert_dff z_test(clk,o,o_p);
endmodule
regression/issue_00350/top.v 0 → 100644
module top (input clk, input i, output o);
reg q = 0;
always @(posedge clk) q <= 1;
assign o = q & i;
endmodule
regression/issue_00361/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [63:0] A, B, C, D = 0;
reg [127:0] E, F = 0;
reg [127:0] X_p, Y_p;
wire [127:0] X,Y;
always @(posedge clk)
begin
A = A + 248;
B = B + 338;
C = C + 435;
D = D + 282;
E = E + 1248;
F = F + 2148;
end
integer i;
always @* begin
X_p = A*B + E;
Y_p = F;
for (i = 0; i < 64; i=i+1)
Y_p = Y_p + C[i]*D[i];
end
top uut (A,B,C,D,E,F,X,Y);
uut_checker X_test(.clk(clk), .A(X), .B(X_p));
uut_checker Y_test(.clk(clk), .A(Y), .B(Y_p));
endmodule
module uut_checker(input clk, input [127:0] A, input [127:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/issue_00361/top.v 0 → 100644
module top (input [63:0] A, B, C, D, input [127:0] E, F, output reg [127:0] X, Y);
integer i;
always @* begin
X = A*B + E;
Y = F;
for (i = 0; i < 64; i=i+1)
Y = Y + C[i]*D[i];
end
endmodule
regression/issue_00362/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [63:0] A, B, C, D = 0;
reg [127:0] E, F = 0;
reg [127:0] X_p, Y_p;
wire [127:0] X,Y;
always @(posedge clk)
begin
A = A + 248;
B = B + 338;
C = C + 435;
D = D + 282;
E = E + 1248;
F = F + 2148;
end
integer i;
always @* begin
X_p = A*B + E;
Y_p = F;
for (i = 0; i < 64; i=i+1)
Y_p = Y_p + C[i]*D[i];
end
top uut (A,B,C,D,E,F,X,Y);
uut_checker X_test(.clk(clk), .A(X), .B(X_p));
uut_checker Y_test(.clk(clk), .A(Y), .B(Y_p));
endmodule
module uut_checker(input clk, input [127:0] A, input [127:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/issue_00362/top.v 0 → 100644
module inst(a,b);
output b;
input a;
assign b = ~a;
endmodule
module top(a,b);
input a;
output b;
inst inst(
.a(a),
.b(1'b1)
);
endmodule
regression/issue_00372/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg d = 0;
wire q;
reg q_p = 0;
always @(posedge clk)
q_p <= d;
top uut (clk,d,q);
assert_dff q_test(clk,q,q_p);
endmodule
regression/issue_00372/top.v 0 → 100644
module top(clk,d,q);
input clk,d;
output reg q;
always @(posedge clk)
if (!1'h1)
q <= 0;
else
q <= d;
endmodule
regression/issue_00391/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (clk);
endmodule
regression/issue_00391/top.v 0 → 100644
module decode1_1(input clk,
input rst,
input [31:0] in_count,
input in_valid,
output in_ready,
input out_ready,
output out_valid);
reg [31:0] r_remaining_count;
reg r_valid;
reg r_ready;
assign out_valid = r_valid;
assign in_ready = r_ready;
always @(posedge clk) begin
if (rst) begin
r_remaining_count <= 0;
r_valid <= 0;
r_ready <= 0;
end else begin
if (r_remaining_count == 0) begin
if (r_ready && in_valid) begin
r_remaining_count <= in_count;
r_valid <= in_count != 0;
r_ready <= 0;
end else begin
r_ready <= 1;
r_valid <= 0;
end
end else begin
r_valid <= !(r_remaining_count == 1 && out_ready && out_valid);
r_ready <= 0;
if (out_valid && out_ready) begin
r_remaining_count <= r_remaining_count - 1;
end
end
end
end
endmodule // decode1_1
module top(input clk);
wire out_valid;
wire [31:0] out_data;
wire out_ready = 1'b1;
reg [31:0] cycles;
wire rst = (cycles < 3);
wire in_ready;
reg [31:0] test_counts [0:1];
reg [31:0] test_index;
wire in_valid = (test_index < 1) && (cycles > 2);
reg [9:0] out_data_index;
always @(posedge clk)
begin
cycles <= cycles + 1;
end
always @(posedge clk)
begin
if (cycles < 1) begin
test_counts[cycles] <= $anyseq;
end
end
initial begin
cycles = 0;
test_index = 0;
end
decode1_1 decoder(clk, rst,
test_counts[test_index],
in_valid,
in_ready,
out_ready,
out_valid);
always @(posedge clk) begin
if (!rst) begin
assert(out_data_index <= 0);
if (in_valid && in_ready) begin
test_index <= test_index + 1;
end
if (out_ready && out_valid) begin
out_data_index <= out_data_index + 1;
end
end
end // always @ (posedge clk)
endmodule
regression/issue_00391/top_clean.v 0 → 100644
module decode1_1(input clk,
input rst,
input [31:0] in_count,
input in_valid,
output in_ready,
input out_ready,
output out_valid);
reg [31:0] r_remaining_count;
reg r_valid;
reg r_ready;
assign out_valid = r_valid;
assign in_ready = r_ready;
always @(posedge clk) begin
if (rst) begin
r_remaining_count <= 0;
r_valid <= 0;
r_ready <= 0;
end else begin
if (r_remaining_count == 0) begin
if (r_ready && in_valid) begin
r_remaining_count <= in_count;
r_valid <= in_count != 0;
r_ready <= 0;
end else begin
r_ready <= 1;
r_valid <= 0;
end
end else begin
r_valid <= !(r_remaining_count == 1 && out_ready && out_valid);
r_ready <= 0;
if (out_valid && out_ready) begin
r_remaining_count <= r_remaining_count - 1;
end
end
end
end
endmodule // decode1_1
module top(input clk);
wire out_valid;
wire [31:0] out_data;
wire out_ready = 1'b1;
reg [31:0] cycles;
wire rst = (cycles < 3);
wire in_ready;
reg [31:0] test_counts [0:1];
reg [31:0] test_index;
wire in_valid = (test_index < 1) && (cycles > 2);
reg [9:0] out_data_index;
always @(posedge clk)
begin
cycles <= cycles + 1;
end
always @(posedge clk)
begin
if (cycles < 1) begin
//test_counts[cycles] <= $anyseq;
end
end
initial begin
cycles = 0;
test_index = 0;
end
decode1_1 decoder(clk, rst,
test_counts[test_index],
in_valid,
in_ready,
out_ready,
out_valid);
always @(posedge clk) begin
if (!rst) begin
// assert(out_data_index <= 0);
if (in_valid && in_ready) begin
test_index <= test_index + 1;
end
if (out_ready && out_valid) begin
out_data_index <= out_data_index + 1;
end
end
end // always @ (posedge clk)
endmodule
regression/issue_00432/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a;
reg [7:0] b;
wire [7:0] c_p;
wire [7:0] c;
always @(posedge clk)
begin
a = a + 3;
b = b + 7;
end
assign c_p = a[$signed(b) +: 8];
top uut (a, b, c);
uut_checker c_test(.clk(clk), .A(c_p), .B(c));
endmodule
module uut_checker(input clk, input [7:0] A, input [7:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/issue_00432/top.v 0 → 100644
module top(a, b, c);
input [7:0] a;
input [7:0] b;
output [7:0] c;
assign c = a[$signed(b) +: 8];
endmodule
regression/issue_00444/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [4:0] a;
wire [31:0] c;
always @(posedge clk)
begin
a = a + 3;
end
top uut (clk, a, c);
uut_checker c_test(.clk(clk), .A(c), .B(c));
endmodule
module uut_checker(input clk, input [31:0] A, input [31:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/issue_00444/top.v 0 → 100644
`ifdef FORMAL
`define assume(_expr_) assume(_expr_)
`else
`define assume(_expr_)
`endif
module top(input clk, input [4:0] addr, output reg [31:0] data);
reg [31:0] mem [0:31];
always @(posedge clk)
data <= mem[addr];
reg [31:0] used_addr = 0;
reg [31:0] used_dbits = 0;
reg initstate = 1;
always @(posedge clk) begin
initstate <= 1;
if (!initstate) begin
//`assume(data != 0);
//`assume((used_dbits & data) == 0);
end
end
endmodule
regression/issue_00449/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire b;
top uut (clk,b);
assert_X b_test(.clk(clk), .A(b));
endmodule
regression/issue_00449/top.v 0 → 100644
module top(i_clk,b);
input i_clk;
output b;
wire value = 0;
reg f_past_gbl_clock_valid;
initial f_past_gbl_clock_valid = 0;
always @(posedge i_clk)
f_past_gbl_clock_valid <= 1'b1;
always @(posedge i_clk)
if ((f_past_gbl_clock_valid)&&(!$rose(i_clk)))
begin
assert($stable(value));
end
assign b = f_past_gbl_clock_valid;
endmodule
regression/issue_00457/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire b;
top uut (clk,b);
assert_X b_test(.clk(clk), .A(b));
endmodule
regression/issue_00457/top.v 0 → 100644
module top(i_clk,b);
input i_clk;
output b;
wire value = 0;
reg f_past_gbl_clock_valid;
initial f_past_gbl_clock_valid = 0;
always @(posedge i_clk)
f_past_gbl_clock_valid <= 1'b1;
function automatic [19:0] zz_coreArea_uartBridge_uartConfigReg_clockDivider(input dummy);
begin
zz_coreArea_uartBridge_uartConfigReg_clockDivider = (20'b00000000000000000000);
zz_coreArea_uartBridge_uartConfigReg_clockDivider = (20'b00000000000000011010);
end
endfunction
assign b = f_past_gbl_clock_valid;
endmodule
regression/issue_00474/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire b;
top uut (clk,b);
assert_X b_test(.clk(clk), .A(b));
endmodule
regression/issue_00474/top.v 0 → 100644
module top(i_clk,b);
input i_clk;
output b;
reg f_past_gbl_clock_valid;
initial f_past_gbl_clock_valid = 0;
always @(posedge i_clk)
f_past_gbl_clock_valid <= 1'b1;
assign b = f_past_gbl_clock_valid;
endmodule
regression/issue_00481/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire b;
top uut (clk,b);
assert_X b_test(.clk(clk), .A(b));
endmodule
regression/issue_00481/top.v 0 → 100644
module top (
input clkIn,
output clkOut
);
// Set up clock for 48Mhz with input of 12MHz
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.PLLOUT_SELECT("GENCLK"),
.DIVR(4'b0000),
.DIVF(7'b0111111),
.DIVQ(3'b100),
.FILTER_RANGE(3'b001)
) uut (
.LOCK(lock),
.RESETB(1'b1),
.BYPASS(1'b0),
.REFERENCECLK(clkIn),
.PLLOUTCORE(clkOut)
);
endmodule
regression/issue_00502/top.v 0 → 100644
module top (A, B, C, Y);
input A, B, C;
output Y;
MY_AND3 inst_t1 (.A(A), .B(B), .C(C), .Y(Y) );
endmodule
module MY_AND3 (A, B, C, Y);
input A, B, C;
output Y;
// MY_AND2 inst_a1 (.A(A), .B(B), .Y(\\SUM/N10) ); // will not read
MY_AND2 inst_a1 (.A(A), .B(B), .Y( \\SUM/N10 ) ); // needs whitespaces around net name
MY_AND2 inst_a2 (.A(C), .B( \\SUM/N10 ), .Y(Y) );
endmodule
module MY_AND2 (A, B, Y);
input A, B;
output Y;
assign Y = A & B;
endmodule
regression/issue_00524/top.v 0 → 100644
module top(
inout a,
inout b,
input dir,
);
wire aout, bout;
GP_IOBUF iobufa(
.IO(a),
.OUT(aout),
.IN(bout),
.OE(dir)
);
GP_IOBUF iobufb(
.IO(b),
.OUT(bout),
.IN(aout),
.OE(!dir)
);
endmodule
regression/issue_00527/osu018_stdcells_edit.lib 0 → 100755
This source diff could not be displayed because it is too large. You can view the blob instead.
regression/issue_00527/sd_rrmux.v 0 → 100644
//----------------------------------------------------------------------
// Srdy/drdy round-robin arbiter
// but without the one cycle decision delay.
//
// This component supports multiple round-robin modes:
//
// Mode 0 : Each input gets a single cycle, regardless of data
// availability. This mode functions like a TDM
// demultiplexer. Output flow control will cause the
// component to stall, so that inputs do not miss their
// turn due to flow control.
// Mode 0 fast arb : Each input gets a single grant. If the
// output is not ready (p_drdy deasserted), then the
// machine will hold on that particular input until it
// receives a grant. Once a single token has been
// accepted the machine will round-robin arbitrate.
// When there are no requests the machine returns to
// its default state.
// Mode 1 : Each input can transmit for as long as it has data.
// When input deasserts, device will begin to hunt for a
// new input with data.
// Mode 2 : Continue to accept input until the incoming data
// matches a particular "end pattern". The end pattern
// is provided on the c_rearb (re-arbitrate) input. When
// c_rearb is high, will hunt for new inputs on next clock.
//
// This component also supports two arbitration modes: slow and fast.
// slow rotates the grant from requestor to requestor cycle by cycle,
// so each requestor gets serviced at most once every #inputs cycles.
// This can be useful for producing a TDM-type interface, however
// requestors may be delayed waiting for the grant to come around even
// if there are no other requestors.
//
// Fast mode immediately grants the highest-priority requestor, however
// it is drdy-noncompliant (drdy will not be asserted until srdy is
// asserted).
//
// Naming convention: c = consumer, p = producer, i = internal interface
//----------------------------------------------------------------------
// Author: Frank Wang
//
// This block is uncopyrighted and released into the public domain.
//----------------------------------------------------------------------
`ifndef _SD_RRMUX_V_
`define _SD_RRMUX_V_
// Clocking statement for synchronous blocks. Default is for
// posedge clocking and positive async reset
`ifndef SDLIB_CLOCKING
`define SDLIB_CLOCKING posedge clk or posedge reset
`endif
// delay unit for nonblocking assigns, default is to #1
`ifndef SDLIB_DELAY
`define SDLIB_DELAY #1
`endif
module sd_rrmux
#(parameter width=8,
parameter inputs=2,
parameter mode=0,
parameter fast_arb=1)
(
input clk,
input reset,
input [(width*inputs)-1:0] c_data,
input [inputs-1:0] c_srdy,
output [inputs-1:0] c_drdy,
input c_rearb, // for use with mode 2 only
output reg [width-1:0] p_data,
output [inputs-1:0] p_grant,
output reg p_srdy,
input p_drdy
);
// bmp for the c_srdy that has just been granted and accepted by p_drdy
reg [inputs-1:0] just_granted;
//control path, transit only after p_drdy ("accepted" part).
reg [inputs-1:0] to_be_granted;
//for data path, regardless of p_drdy, help to remove combo loops
//rational being, when p_drdy==1'b0, it doesn't matter what p_data is.
reg [inputs-1:0] to_tx_data;
wire [width-1:0] rr_mux_grid [0:inputs-1];
reg rr_locked;
reg nxt_rr_locked; // ri lint_check_waive NOT_DRIVEN
genvar i;
integer j;
assign c_drdy = to_be_granted & {inputs{p_drdy}};
assign p_grant = to_be_granted;
function [inputs-1:0] nxt_grant;
input [inputs-1:0] cur_grant;
input [inputs-1:0] cur_req;
input cur_accept;
reg [inputs-1:0] msk_req;
reg [inputs-1:0] tmp_grant;
reg [inputs-1:0] tmp_grant2;
begin
// scenario:
// in cycle 0, src 1 is granted and accepted by p_drdy,
// in cycle 1, src 3 is requesting, but p_drdy is 0, so c_data3 is presented at p_data with p_srdy
// in cycle 2, if src 2 comes in requesting, should hold src 3 at p_data till p_drdy,
// src 2 will only participate in next round arb.
// the way is in this scenario, pretend src2 is the just_granted in cycle 1.
// so arbitration is excercies in two cases: (1): p_drdy,
// or (2) p_not_drdy, the immediate next c_not_srdy, but at least one remote c_srdy
msk_req = cur_req & ~((cur_grant - 1) | cur_grant);
tmp_grant = msk_req & (~msk_req + 1);
tmp_grant2 = cur_req & (~cur_req + 1);
if(cur_accept)begin
if (msk_req != 0) nxt_grant = tmp_grant;
else nxt_grant = tmp_grant2;
//end else if (rem_neighbor_rearb) begin
end else if (| cur_req) begin
if (msk_req != 0) nxt_grant = {tmp_grant[0],tmp_grant[inputs-1:1]};
else nxt_grant = {tmp_grant2[0],tmp_grant2[inputs-1:1]};
end else begin
nxt_grant = cur_grant;
end
end
endfunction
generate
for (i=0; i<inputs; i=i+1)
begin : grid_assign
//assign rr_mux_grid[i] = c_data >> (i*width);
assign rr_mux_grid[i] = c_data[i*width+width-1 : i*width];
end
if (mode == 2)
begin : tp_gen
always @*
begin
nxt_rr_locked = rr_locked;
if ((c_srdy & just_granted) & (!rr_locked))
nxt_rr_locked = 1;
else if ((c_srdy & just_granted & c_rearb))
nxt_rr_locked = 0;
end
always @(`SDLIB_CLOCKING)
begin
if (reset)
rr_locked <= 0;
else
rr_locked <= nxt_rr_locked;
end
end // block: tp_gen
endgenerate
// always @*
// begin
// p_data = 0;
// p_srdy = 0;
// for (j=0; j<inputs; j=j+1)
// if (just_granted[j])
// begin
// p_data = rr_mux_grid[j];
// p_srdy = c_srdy[j];
// end
// end
always @(*) begin
p_srdy = | c_srdy;
p_data = {width{1'b0}};
for (j=0; j<inputs; j=j+1) begin
if (to_tx_data[j]) begin
p_data = rr_mux_grid[j];
p_srdy = c_srdy[j];
end
end
end
always @*
begin
to_tx_data = just_granted;
to_be_granted = just_granted;
if ((mode == 1) & (|(c_srdy & just_granted)))
to_be_granted = just_granted;
else if ((mode == 0) && !fast_arb)begin
to_be_granted=p_drdy?{just_granted[0],just_granted[inputs-1:1]}:just_granted;
to_tx_data={just_granted[0],just_granted[inputs-1:1]};
end
//else if ((mode == 0) && |(just_granted & c_srdy) && !p_drdy && fast_arb)
// to_be_granted = just_granted;
else if ((mode == 2) & (nxt_rr_locked | (|(c_srdy & just_granted))))
to_be_granted = just_granted;
else if (fast_arb) begin
to_be_granted=nxt_grant (just_granted, c_srdy, p_drdy);
to_tx_data = nxt_grant(just_granted, c_srdy, 1'b1);
end
else begin
to_be_granted=p_drdy?{just_granted[0],just_granted[inputs-1:1]}:just_granted;
to_tx_data={just_granted[0],just_granted[inputs-1:1]};
end
end
always @(`SDLIB_CLOCKING)
begin
if (reset)
just_granted <= {1'b1,{inputs-1{1'b0}}};
else
if (to_be_granted==0)
just_granted <= just_granted;
else
just_granted <= to_be_granted;
end
endmodule
`endif // _SD_RRMUX_V_
regression/issue_00527/syn.tcl 0 → 100644
# Basic synthesis file to replicate DFFSR bug
yosys -import
set libfile osu018_stdcells_edit.lib
read_verilog -sv sd_rrmux.v
# Vanilla synth flow
hierarchy
procs
fsm
opt
techmap
opt
dfflibmap -liberty $libfile
abc -liberty $libfile
clean
write_verilog sd_rrmux_osu.gv
regression/issue_00527/testcase 0 → 100644
#!/bin/bash
yosys -t syn.tcl
if grep -q DFFSR sd_rrmux_osu.gv; then
echo "FAILED -- DFFSR present in netlist"
else
echo "PASSED -- DFFSR not present"
fi
regression/run.sh
......@@ -2,41 +2,97 @@
set -ex
test -d $1
if [ "$2" != "verify" -a "$2" != "falsify" ]; then
test -f scripts/$2.ys
fi
test -f scripts/$2.ys
rm -rf $1/work_$2
mkdir $1/work_$2
cd $1/work_$2
if [ "$2" = "verify" ]; then
iverilog -g 2012 -o testbench ../testbench.v ../../common.v ../top.v ../../../../../techlibs/xilinx/brams_bb.v
elif [ "$2" = "falsify" ]; then
iverilog -DBUG -g 2012 -o testbench ../testbench.v ../../common.v ../top.v ../../../../../techlibs/xilinx/brams_bb.v
else
yosys -ql yosys.log ../../scripts/$2.ys
iverilog -o testbench ../testbench.v ../../common.v synth.v $(yosys-config --datdir/simcells.v) ../../../../../techlibs/xilinx/brams_bb.v
fi
if [ "$2" = "falsify" ]; then
if vvp -N testbench > testbench.log 2>&1; then
echo FAIL > ${1}_${2}.status
elif ! grep 'ERROR' testbench.log || grep 'OKAY' testbench.log; then
echo FAIL > ${1}_${2}.status
# cases where 'syntax error' or other errors are expected
if [ "$1" = "issue_00089" ] ||\
[ "$1" = "issue_00093" ] ||\
[ "$1" = "issue_00095" ] ||\
[ "$1" = "issue_00096" ] ||\
[ "$1" = "issue_00196" ] ||\
[ "$1" = "issue_00362" ]; then
expected_string="syntax error"
#Change checked string for check other errors
if [ "$1" = "issue_00196" ]; then
expected_string="Found posedge/negedge event"
elif [ "$1" = "issue_00362" ]; then
expected_string="is connected to constants:"
fi
if yosys -ql yosys.log ../../scripts/$2.ys; then
echo fail > ${1}_${2}.status
else
if grep "$expected_string" yosys.log; then
echo pass > ${1}_${2}.status
else
echo fail > ${1}_${2}.status
fi
fi
# cases where some object names are/aren't expected in output file (tee -o result.log in the test script)
elif [ "$1" = "issue_00502" ] ||\
[ "$1" = "issue_00524" ] ||\
[ "$1" = "issue_00527" ]; then
expected_string=""
expected="1"
if [ "$1" = "issue_00502" ]; then
expected_string="\\SUM/N10"
elif [ "$1" = "issue_00524" ]; then
expected_string="GP_INV"
elif [ "$1" = "issue_00527" ]; then
expected_string="DFFSR"
expected="0"
fi
yosys -ql yosys.log ../../scripts/$2.ys;
if grep "$expected_string" result.log; then
if [ $expected = "1" ]; then
echo pass > ${1}_${2}.status
else
echo fail > ${1}_${2}.status
fi
else
if [ $expected = "1" ]; then
echo fail > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
fi
fi
# cases with simulation checks
else
iverilog_adds=""
#Additional sources for iverilog simulation
if [ "$1" = "issue_00084" ]; then
iverilog_adds="../../../../../techlibs/xilinx/brams_bb.v"
elif [ "$1" = "issue_00160" ] ||\
[ "$1" = "issue_00182" ] ||\
[ "$1" = "issue_00183" ] ||\
[ "$1" = "issue_00481" ]; then
iverilog_adds="../../../../../techlibs/ice40/cells_sim.v"
fi
yosys -ql yosys.log ../../scripts/$2.ys
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/common/simlib.v $iverilog_adds
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo FAIL > ${1}_${2}.status
echo fail > ${1}_${2}.status
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo FAIL > ${1}_${2}.status
echo fail > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
fi
fi
touch .stamp
regression/scripts/issue_00114.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00126.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00128.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00132.ys 0 → 100644
read_verilog -defer ../top.v
chparam -set incr 42 topmod
synth -top top
write_verilog synth.v
regression/scripts/issue_00133.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00134.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce; clean; opt
write_verilog -noexpr -norename synth.v
regression/scripts/issue_00160.ys 0 → 100644
read_verilog ../top.v
synth_ice40 -top top
write_verilog synth.v
regression/scripts/issue_00171.ys 0 → 100644
read_verilog ../top.v
proc; opt; fsm; opt; memory; opt; techmap; opt
scc -all_cell_types
#and then put each found SCC into a module using submod.
scc -all_cell_types
synth -top top
write_verilog synth.v
regression/scripts/issue_00173.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00174.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
write_verilog -noattr t1.v
proc
opt -full
techmap
abc -lut 6
synth -top top
write_verilog synth.v
regression/scripts/issue_00175.ys 0 → 100644
read_verilog ../top.v
hierarchy
proc
opt
memory
opt
fsm
setundef -zero
opt -full -fine
setundef -zero
opt -full -fine
synth -top top
write_verilog synth.v
regression/scripts/issue_00182.ys 0 → 100644
read_verilog ../top.v
synth_ice40 -blif litescope.bli -top top
write_verilog synth.v
regression/scripts/issue_00183.ys 0 → 100644
read_verilog ../top.v
synth_ice40 -top top -blif test.blif
write_verilog synth.v
regression/scripts/issue_00186.ys 0 → 100644
read_verilog -DTEST_1 ../top.v
hierarchy -top top
proc
memory
opt -full
techmap
write_verilog -noattr synth.v
regression/scripts/issue_00194.ys 0 → 100644
read_verilog ../top.v
proc
prep -flatten
write_verilog synth.v
regression/scripts/issue_00195.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00196.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -json 3pdrive.json
write_verilog synth.v
regression/scripts/issue_00210.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00253.ys 0 → 100644
read_verilog ../top.v
proc; opt; fsm -encoding binary
techmap; opt; stat
write_verilog synth.v
regression/scripts/issue_00282.ys 0 → 100644
read_verilog ../top.v
synth -top top
#synth_ice40 -blif litescope.bli -top top
write_verilog synth.v
regression/scripts/issue_00283.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00287.ys 0 → 100644
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00289.ys 0 → 100644
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00291.ys 0 → 100644
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00300.ys 0 → 100644
read_verilog ../top.v
proc
opt
stat
dump
write_ilang foo.ilang
memory_collect
stat
dump t:$mem
design -reset
read_ilang foo.ilang
stat
memory_collect
dump t:$mem
write_verilog synth.v
regression/scripts/issue_00306.ys 0 → 100644
read_verilog ../top.v
proc
opt -full
synth -top top
write_verilog synth.v
regression/scripts/issue_00314.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00317.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00341.ys 0 → 100644
read_verilog ../top.v
equiv_make gold top_w equiv
hierarchy -top equiv
opt -purge
equiv_simple
equiv_status -assert
design -reset
read_verilog ../top.v
synth
write_verilog synth.v
regression/scripts/issue_00342.ys 0 → 100644
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00349.ys 0 → 100644
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00350.ys 0 → 100644
read_verilog -sv ../top.v
synth -top top
abc -clk clk -g AND
opt
write_verilog synth.v
regression/scripts/issue_00361.ys 0 → 100644
read_verilog -sv ../top.v
prep
alumacc
maccmap -unmap
synth -top top
write_verilog synth.v
regression/scripts/issue_00362.ys 0 → 100644
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00372.ys 0 → 100644
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00391.ys 0 → 100644
read_verilog -sv ../top.v
prep -top top -nordff
write_smt2 top.smt2
design -reset
read_verilog -sv ../top_clean.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00432.ys 0 → 100644
read_verilog -sv ../top.v
proc
hierarchy -check
synth -top top
write_verilog synth.v
regression/scripts/issue_00444.ys 0 → 100644
read_verilog -formal ../top.v
hierarchy
proc_init
proc_mux
proc_dff
proc_clean
opt_clean
opt_merge
opt_rmdff
opt_clean
opt_expr
opt_rmdff
memory
synth -top top
write_verilog synth.v
regression/scripts/issue_00449.ys 0 → 100644
read_verilog -formal ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00457.ys 0 → 100644
read_verilog -formal ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00474.ys 0 → 100644
read_verilog -formal ../top.v
verilog_defaults -push
verilog_defaults -pop
synth -top top
write_verilog synth.v
regression/scripts/issue_00481.ys 0 → 100644
read_verilog ../top.v
synth_ice40 -blif tlt.blif -top top
write_verilog synth.v
regression/scripts/issue_00502.ys 0 → 100644
read_verilog ../top.v
select n:\\SUM/N10
tee -o result.log select -list
regression/scripts/issue_00524.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -part SLG46621V
select GP_INV
tee -o result.log select -list
regression/scripts/issue_00527.ys 0 → 100644
# Basic synthesis file to replicate DFFSR bug
#yosys -import
#set libfile osu018_stdcells_edit.lib
read_verilog -sv ../sd_rrmux.v
# Vanilla synth flow
hierarchy
proc
fsm
opt
techmap
opt
dfflibmap -liberty ../osu018_stdcells_edit.lib
abc -liberty ../osu018_stdcells_edit.lib
clean
select DFFSR
tee -o result.log select -list
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