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yosys-tests
Commit 45c0ea8c by SergeyDegtyar
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Review and update tests for issues 253-432

parent 1098cea6
Showing with 300 additions and 1294 deletions
regression/Makefile
......@@ -20,63 +20,6 @@ endef
#issue_00790
$(eval $(call template,issue_00790,issue_00790))
#issue_00253
$(eval $(call template,issue_00253,issue_00253))
#issue_00282
$(eval $(call template,issue_00282,issue_00282))
#issue_00283
$(eval $(call template,issue_00283,issue_00283))
#issue_00287
$(eval $(call template,issue_00287,issue_00287))
#issue_00289
$(eval $(call template,issue_00289,issue_00289))
#issue_00291
$(eval $(call template,issue_00291,issue_00291))
#issue_00300
$(eval $(call template,issue_00300,issue_00300))
#issue_00306
$(eval $(call template,issue_00306,issue_00306))
#issue_00314
$(eval $(call template,issue_00314,issue_00314))
#issue_00317
$(eval $(call template,issue_00317,issue_00317))
#issue_00341
$(eval $(call template,issue_00341,issue_00341))
#issue_00342
$(eval $(call template,issue_00342,issue_00342))
#issue_00349
$(eval $(call template,issue_00349,issue_00349))
#issue_00350
$(eval $(call template,issue_00350,issue_00350))
#issue_00361
$(eval $(call template,issue_00361,issue_00361))
#issue_00362
$(eval $(call template,issue_00362,issue_00362))
#issue_00372
$(eval $(call template,issue_00372,issue_00372))
#issue_00391
$(eval $(call template,issue_00391,issue_00391))
#issue_00432
$(eval $(call template,issue_00432,issue_00432))
#issue_00444
$(eval $(call template,issue_00444,issue_00444))
......@@ -368,9 +311,6 @@ $(eval $(call template,issue_01372,issue_01372))
#Still open bugs (should be failed):
#issue_00329
$(eval $(call template,issue_00329,issue_00329))
#issue_00623
$(eval $(call template,issue_00623,issue_00623))
......
regression/issue_00253/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [3:0] in = 2;
reg [1:0] count = 0;
reg init = 0;
wire [7:0] out;
always @(posedge clk)
begin
in = in + 7;
count = count + 1;
if (count == 2'b11)
init = 1;
end
top uut(clk,in,out);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
check_X check_output(clk,init,out[index]);
end
endgenerate
endmodule
module check_X(input clk,input init, input A);
always @(posedge clk)
begin
#1;
if (A === 1'bX && init == 1'b1)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00282/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [3:0] in = 2;
reg [1:0] count = 0;
reg init = 0;
wire [7:0] out;
always @(posedge clk)
begin
in = in + 7;
count = count + 1;
if (count == 2'b11)
init = 1;
end
top uut(clk,in,out);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
check_X check_output(clk,init,out[index]);
end
endgenerate
endmodule
module check_X(input clk,input init, input A);
always @(posedge clk)
begin
#1;
if (A === 1'bX && init == 1'b1)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00282/top.v deleted 100644 → 0
module top(input clk,input[3:0] in, output [7:0] out);
reg[2:0] state;
always @(posedge clk) begin
out<=0;
case (state)
0: begin
if(in == 0) begin
state<=1;
out<=0;
end
if(in == 1) begin
state<=2;
out<=1;
end
if(in == 2) begin
state<=5;
out<=2;
end
end
1: begin
if(in == 0) begin
state<=1;
out<=3;
end
if(in == 1) begin
state<=3;
out<=4;
end
if(in == 2) begin
state<=1;
out<=5;
end
if(in == 3) begin
state<=3;
out<=6;
end
if(in == 4) begin
state<=2;
out<=7;
end
if(in == 5) begin
state<=5;
out<=8;
end
if(in == 6) begin
state<=3;
out<=9;
end
if(in == 7) begin
state<=5;
out<=10;
end
if(in == 8) begin
state<=3;
out<=11;
end
if(in == 9) begin
state<=2;
out<=12;
end
end
2: begin
if(in == 0) begin
state<=2;
out<=13;
end
if(in == 1) begin
state<=2;
out<=14;
end
if(in == 2) begin
state<=1;
out<=15;
end
if(in == 3) begin
state<=1;
out<=16;
end
if(in == 4) begin
state<=2;
out<=17;
end
if(in == 5) begin
state<=2;
out<=18;
end
if(in == 6) begin
state<=2;
out<=19;
end
if(in == 7) begin
state<=5;
out<=20;
end
if(in == 8) begin
state<=5;
out<=21;
end
if(in == 9) begin
state<=2;
out<=22;
end
end
3: begin
if(in == 0) begin
state<=3;
out<=23;
end
if(in == 1) begin
state<=3;
out<=24;
end
if(in == 2) begin
state<=3;
out<=25;
end
if(in == 3) begin
state<=3;
out<=26;
end
if(in == 4) begin
state<=4;
out<=27;
end
if(in == 5) begin
state<=5;
out<=28;
end
if(in == 6) begin
state<=3;
out<=29;
end
if(in == 7) begin
state<=5;
out<=30;
end
if(in == 8) begin
state<=3;
out<=31;
end
if(in == 9) begin
state<=2;
out<=32;
end
end
4: begin
if(in == 0) begin
state<=4;
out<=33;
end
if(in == 1) begin
state<=4;
out<=34;
end
if(in == 2) begin
state<=3;
out<=35;
end
if(in == 3) begin
state<=3;
out<=36;
end
if(in == 4) begin
state<=4;
out<=37;
end
if(in == 5) begin
state<=2;
out<=38;
end
if(in == 6) begin
state<=2;
out<=39;
end
if(in == 7) begin
state<=5;
out<=40;
end
if(in == 8) begin
state<=5;
out<=41;
end
if(in == 9) begin
state<=2;
out<=42;
end
end
5: begin
if(in == 0) begin
state<=1;
out<=43;
end
if(in == 1) begin
state<=1;
out<=44;
end
if(in == 2) begin
state<=1;
out<=45;
end
if(in == 3) begin
state<=1;
out<=46;
end
if(in == 4) begin
state<=2;
out<=47;
end
if(in == 5) begin
state<=5;
out<=48;
end
if(in == 6) begin
state<=5;
out<=49;
end
if(in == 7) begin
state<=5;
out<=50;
end
if(in == 8) begin
state<=5;
out<=51;
end
if(in == 9) begin
state<=2;
out<=52;
end
end
endcase
end
endmodule
regression/issue_00283/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire y;
top uut(clk,1'b1,y);
assert_X check_output(clk,y);
endmodule
regression/issue_00283/top.v deleted 100644 → 0
module top(input clk, enable, output reg y);
wire [1:0] foo [1:0];
integer i;
initial begin
for (i=0;i<=1;i=i+1)
foo[i] = 2'b11;
end
always @(posedge clk)
if (enable)
for (i = 0; i < 2; i=i+1)
y <= foo[0][0];
endmodule
regression/issue_00287/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [6:0] D = 0;
reg [1:0] S = 0;
wire [1:0] Y;
reg [1:0] Y_p;
always @(posedge clk)
begin
D = D + 3;
S = S + 1;
end
always @* begin : block
reg [3:0] data [0:3];
data[0] = D[3:0];
data[1] = D[4:1];
data[2] = D[5:2];
data[3] = D[6:3];
Y_p = data[S];
end
top uut(D,S,Y);
assert_dff check_Y0 (clk,Y[0],Y_p[0]);
assert_dff check_Y1 (clk,Y[1],Y_p[1]);
endmodule
regression/issue_00289/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire o;
top uut(clk,o);
assert_dff check_o (clk,clk,o);
endmodule
regression/issue_00291/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg rst = 0;
reg any_pop = 0;
reg any_push = 0;
always @(posedge clk)
begin
rst = 1;
#1
any_pop = ~any_pop;
#3
any_push = ~any_push;
end
top uut(rst,clk,any_push,any_pop);
endmodule
regression/issue_00300/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] addr = 0;
reg [7:0] wdata = 0;
wire [7:0] rdata;
wire [7:0] rdata_o;
always @(posedge clk)
begin
addr = addr + 1;
wdata = wdata + 17;
end
reg [7:0] memory [255:0];
assign rdata = memory[addr];
always @(posedge clk) memory[addr] <= wdata;
top uut(clk,addr,wdata,rdata_o);
uut_mem_checker port_b_test(.clk(clk), .A(rdata), .B(rdata_o));
endmodule
module uut_mem_checker(input clk, input [7:0] A, input [7:0] B);
always @(posedge clk)
begin
#1;
if (A == B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/issue_00306/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [3:0] a = 0;
wire res_p;
wire res;
always @(posedge clk)
begin
a = a + 1;
end
assign res_p = a < 6'b100000;
top uut(a,res);
assert_dff check_res (clk,res, res_p);
endmodule
regression/issue_00314/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
reg [7:0] b = 0;
wire [7:0] z;
always @(posedge clk)
begin
a = a + 1;
b = b + 7;
end
top uut(a,b,z);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
assert_Z check_output(clk,z[index]);
end
endgenerate
endmodule
regression/issue_00317/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] in = 0;
wire [7:0] out;
always @(posedge clk) begin
in <= in + 1;
end
top uut (
.alu_data_d_in (in ),
.alu_data_d_out (out )
);
uut_checker q_test(.clk(clk), .A(out));
endmodule
module uut_checker(input clk, input [7:0] A);
always @(posedge clk)
begin
#1;
if (A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00341/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i1,i2 = 0;
wire o1g,o2g;
wire o1r,o2r;
wire o1w,o2w;
wire o1gt,o2gt;
wire o1rt,o2rt;
wire o1wt,o2wt;
always @(posedge clk) begin
i1 <= i1 + 1;
i2 <= i2 + 1;
end
gold uut_g (
i1,i2,o1g,o2g
);
top_r uut_r (
i1,i2,o1r,o2r
);
top_w uut_w (
i1,i2,o1w,o2w
);
goldt uut_gt (
i1,i2,o1gt,o2gt
);
top_rt uut_rt (
i1,i2,o1rt,o2rt
);
top_wt uut_wt (
i1,i2,o1wt,o2wt
);
assert_dff gold_test(clk,o1g,o1gt);
assert_dff top_r_test(clk,o1r,o1rt);
assert_dff top_w_test(clk,o1w,o1wt);
endmodule
module goldt(input i1, input i2, output o2, output o1);
wire _1_;
assign o2 = i1 & i2;
assign _1_ = i1 | i2;
assign o1 = _1_ & o2;
endmodule
module top_rt( i1, i2, o1, o2 );
input i1, i2;
output o1, o2;
wire w4;
assign o2 = (i2 & i1);
assign w4 = ((i2 && i1) | (i2) | (i1));
assign o1 = ((w4 & o2));
endmodule
module top_wt( i1, i2, o1, o2 );
input i1, i2;
output o1, o2;
wire w4;
assign o2 = (i2 & i1);
assign w4 = ((i2 & i1) | (i2) | (i1));
assign o1 = ((w4 & o2));
endmodule
regression/issue_00342/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] addr = 0;
reg [7:0] wdata = 0;
wire [7:0] rdata;
wire [7:0] rdata_o;
always @(posedge clk)
begin
addr = addr + 1;
wdata = wdata + 17;
end
logic [8-1:0] mem [8-1:0];
assign rdata_o = mem[addr];
always @*
if (clk)
mem[addr] <= wdata;
top uut(rdata,wdata,addr,clk,clk);
uut_mem_checker port_b_test(.clk(clk), .A(rdata), .B(rdata_o));
endmodule
module uut_mem_checker(input clk, input [7:0] A, input [7:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/issue_00349/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] in = 0;
reg z_p;
wire z;
always @(posedge clk) begin
in <= in + 1;
end
always @*
z_p <= in[0] ~& in[1];
top uut (in[0],in[1],z);
assert_dff z_test(clk,z,z_p);
endmodule
regression/issue_00350/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i;
wire o_p;
wire o;
always @(posedge clk) begin
#2
i <= ~i;
end
reg q = 0;
always @(posedge clk) q <= 1;
assign o_p = q & i;
top uut (clk,i,o);
assert_dff z_test(clk,o,o_p);
endmodule
regression/issue_00350/top.v deleted 100644 → 0
module top (input clk, input i, output o);
reg q = 0;
always @(posedge clk) q <= 1;
assign o = q & i;
endmodule
regression/issue_00361/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [63:0] A, B, C, D = 0;
reg [127:0] E, F = 0;
reg [127:0] X_p, Y_p;
wire [127:0] X,Y;
always @(posedge clk)
begin
A = A + 248;
B = B + 338;
C = C + 435;
D = D + 282;
E = E + 1248;
F = F + 2148;
end
integer i;
always @* begin
X_p = A*B + E;
Y_p = F;
for (i = 0; i < 64; i=i+1)
Y_p = Y_p + C[i]*D[i];
end
top uut (A,B,C,D,E,F,X,Y);
uut_checker X_test(.clk(clk), .A(X), .B(X_p));
uut_checker Y_test(.clk(clk), .A(Y), .B(Y_p));
endmodule
module uut_checker(input clk, input [127:0] A, input [127:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/issue_00362/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [63:0] A, B, C, D = 0;
reg [127:0] E, F = 0;
reg [127:0] X_p, Y_p;
wire [127:0] X,Y;
always @(posedge clk)
begin
A = A + 248;
B = B + 338;
C = C + 435;
D = D + 282;
E = E + 1248;
F = F + 2148;
end
integer i;
always @* begin
X_p = A*B + E;
Y_p = F;
for (i = 0; i < 64; i=i+1)
Y_p = Y_p + C[i]*D[i];
end
top uut (A,B,C,D,E,F,X,Y);
uut_checker X_test(.clk(clk), .A(X), .B(X_p));
uut_checker Y_test(.clk(clk), .A(Y), .B(Y_p));
endmodule
module uut_checker(input clk, input [127:0] A, input [127:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/issue_00372/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg d = 0;
wire q;
reg q_p = 0;
always @(posedge clk)
q_p <= d;
top uut (clk,d,q);
assert_dff q_test(clk,q,q_p);
endmodule
regression/issue_00391/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (clk);
endmodule
regression/issue_00391/top_clean.v deleted 100644 → 0
module decode1_1(input clk,
input rst,
input [31:0] in_count,
input in_valid,
output in_ready,
input out_ready,
output out_valid);
reg [31:0] r_remaining_count;
reg r_valid;
reg r_ready;
assign out_valid = r_valid;
assign in_ready = r_ready;
always @(posedge clk) begin
if (rst) begin
r_remaining_count <= 0;
r_valid <= 0;
r_ready <= 0;
end else begin
if (r_remaining_count == 0) begin
if (r_ready && in_valid) begin
r_remaining_count <= in_count;
r_valid <= in_count != 0;
r_ready <= 0;
end else begin
r_ready <= 1;
r_valid <= 0;
end
end else begin
r_valid <= !(r_remaining_count == 1 && out_ready && out_valid);
r_ready <= 0;
if (out_valid && out_ready) begin
r_remaining_count <= r_remaining_count - 1;
end
end
end
end
endmodule // decode1_1
module top(input clk);
wire out_valid;
wire [31:0] out_data;
wire out_ready = 1'b1;
reg [31:0] cycles;
wire rst = (cycles < 3);
wire in_ready;
reg [31:0] test_counts [0:1];
reg [31:0] test_index;
wire in_valid = (test_index < 1) && (cycles > 2);
reg [9:0] out_data_index;
always @(posedge clk)
begin
cycles <= cycles + 1;
end
always @(posedge clk)
begin
if (cycles < 1) begin
//test_counts[cycles] <= $anyseq;
end
end
initial begin
cycles = 0;
test_index = 0;
end
decode1_1 decoder(clk, rst,
test_counts[test_index],
in_valid,
in_ready,
out_ready,
out_valid);
always @(posedge clk) begin
if (!rst) begin
// assert(out_data_index <= 0);
if (in_valid && in_ready) begin
test_index <= test_index + 1;
end
if (out_ready && out_valid) begin
out_data_index <= out_data_index + 1;
end
end
end // always @ (posedge clk)
endmodule
regression/issue_00432/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a;
reg [7:0] b;
wire [7:0] c_p;
wire [7:0] c;
always @(posedge clk)
begin
a = a + 3;
b = b + 7;
end
assign c_p = a[$signed(b) +: 8];
top uut (a, b, c);
uut_checker c_test(.clk(clk), .A(c_p), .B(c));
endmodule
module uut_checker(input clk, input [7:0] A, input [7:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/scripts/issue_00253.ys deleted 100644 → 0
read_verilog ../top.v
proc; opt; fsm -encoding binary
techmap; opt; stat
write_verilog synth.v
regression/scripts/issue_00282.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
#synth_ice40 -blif litescope.bli -top top
write_verilog synth.v
regression/scripts/issue_00350.ys deleted 100644 → 0
read_verilog -sv ../top.v
synth -top top
abc -clk clk -g AND
opt
write_verilog synth.v
regression/scripts/issue_00372.ys deleted 100644 → 0
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00432.ys deleted 100644 → 0
read_verilog -sv ../top.v
proc
hierarchy -check
synth -top top
write_verilog synth.v
regression_revised/Makefile
......@@ -150,4 +150,65 @@ $(eval $(call template,issue_00196,issue_00196_fail))
#issue_00210
$(eval $(call template,issue_00210,issue_00210))
#issue_00253
$(eval $(call template,issue_00253,issue_00253))
#issue_00282
$(eval $(call template,issue_00282,issue_00282))
#issue_00283
$(eval $(call template,issue_00283,issue_00283))
#issue_00287
$(eval $(call template,issue_00287,issue_00287))
#issue_00289
$(eval $(call template,issue_00289,issue_00289))
#issue_00291
$(eval $(call template,issue_00291,issue_00291))
#issue_00300
$(eval $(call template,issue_00300,issue_00300))
#issue_00306
$(eval $(call template,issue_00306,issue_00306))
#issue_00314
$(eval $(call template,issue_00314,issue_00314))
#issue_00317
$(eval $(call template,issue_00317,issue_00317))
#issue_00341
$(eval $(call template,issue_00341,issue_00341))
#issue_00342
$(eval $(call template,issue_00342,issue_00342))
#issue_00349
$(eval $(call template,issue_00349,issue_00349))
#issue_00350
$(eval $(call template,issue_00350,issue_00350))
#issue_00361
$(eval $(call template,issue_00361,issue_00361))
#issue_00362
$(eval $(call template,issue_00362,issue_00362_fail))
#issue_00372
$(eval $(call template,issue_00372,issue_00372))
#issue_00391
$(eval $(call template,issue_00391,issue_00391))
#issue_00432
$(eval $(call template,issue_00432,issue_00432))
#Still open bugs (should be failed):
#issue_00329
$(eval $(call template,issue_00329,issue_00329))
.PHONY: all clean
regression_revised/issue_00253/issue_00253.pat 0 → 100644
State encoding:
0: 3'100
1: 3'010
2: 3'001
3: 3'101
4: 3'011
regression_revised/issue_00253/issue_00253.ys 0 → 100644
read_verilog ../top.v
proc; opt
tee -o result.out fsm -encoding binary
techmap; opt
regression/scripts/issue_00314.ys → regression_revised/issue_00282/issue_00282.ys
read_verilog ../top.v
synth -top top
write_verilog synth.v
#synth_ice40 -top top
select -assert-count 1 t:$_DFF_P_
regression_revised/issue_00282/top.v 0 → 100644
module top(input clk,input in, output out);
always @(posedge clk)
out<=in;
endmodule
regression_revised/issue_00283/top.v 0 → 100644
module top
#(parameter WIDTH = 64, C_WIDTH = 8, DE = 4)
(
input clk,
input reset,
input [C_WIDTH*WIDTH-1:0] c_data_in_port,
input [DE*C_WIDTH -1:0] d_one_hot,
input [C_WIDTH -1:0] c_data_in_en,
output reg [DE*WIDTH-1:0] d_data_out_port,
output reg [DE-1:0] d_data_out_en
);
reg [ WIDTH-1:0] clients_data_in [ C_WIDTH-1:0];
reg [ C_WIDTH-1:0] devices_one_hot_client_sel [ DE-1:0];
reg [ WIDTH-1:0] devices_data_out [ DE-1:0];
reg [ WIDTH-1:0] clients_data_in_s [ C_WIDTH-1:0];
reg [ C_WIDTH-1:0] devices_one_hot_client_sel_s [ DE-1:0];
wire [ WIDTH-1:0] devices_data_out_p [ DE-1:0];
wire [ C_WIDTH-1:0] clients_data_rotate [ WIDTH-1:0];
wire [ DE-1:0] devices_data_rotate [ WIDTH-1:0];
reg [ DE-1:0] clients_one_hot_device_sel [ C_WIDTH-1:0];
wire [ DE-1:0] dev_en;
wire [ DE-1:0] data_out_en;
integer client, device;
always @*
begin
for(client = 0; client < C_WIDTH; client = client + 1) begin
clients_data_in[client] = c_data_in_port[client*WIDTH+:WIDTH];
end
end
always @*
begin
for(client = 0; client < C_WIDTH; client = client + 1) begin
clients_one_hot_device_sel[client] = d_one_hot[client*DE+:DE];
end
end
always @*
begin
for (device = 0; device < DE; device = device + 1) begin
for(client = 0; client < C_WIDTH; client = client + 1) begin
devices_one_hot_client_sel[device][client] = clients_one_hot_device_sel[client][device];
end
end
end
genvar k;
integer rowsel;
genvar i, j, nw;
always @(posedge clk or negedge reset)
if (!reset)
for (rowsel = 0; rowsel < DE; rowsel=rowsel+1)
devices_data_out[rowsel][WIDTH-1:1] <= 'b0;
else begin
for (rowsel = 0; rowsel < DE; rowsel=rowsel+1)
if (dev_en[rowsel]==1'b1)
devices_data_out[rowsel][WIDTH-1:1] <= devices_data_out_p[rowsel][WIDTH-1:1];
end
always @(posedge clk or negedge reset)
if (!reset)
for (rowsel = 0; rowsel < DE; rowsel=rowsel+1)
devices_data_out[rowsel][0] <= 1'b0;
else
for (rowsel = 0; rowsel < DE; rowsel=rowsel+1)
devices_data_out[rowsel][0] <= devices_data_out_p[rowsel][0];
always @*
begin
for(rowsel = 0; rowsel < C_WIDTH; rowsel=rowsel+1) begin
clients_data_in_s[rowsel][WIDTH-1:0] = clients_data_in[rowsel];
end
end
always @*
begin
for(rowsel = 0; rowsel < DE; rowsel=rowsel+1) begin
devices_one_hot_client_sel_s[rowsel][C_WIDTH-1:0] = devices_one_hot_client_sel[rowsel][C_WIDTH-1:0];
end
end
generate
for (i = 0; i < DE; i=i+1) begin:gen_i3
assign dev_en[i] = |devices_one_hot_client_sel_s[i][C_WIDTH-1:0];
end
endgenerate
generate
for (i = 0; i < DE; i=i+1) begin:gen_i4
assign data_out_en[i] = |devices_one_hot_client_sel[i][C_WIDTH-1:0];
end
endgenerate
always @(posedge clk or negedge reset)
if (!reset)
for (rowsel = 0; rowsel < DE; rowsel=rowsel+1)
d_data_out_en[rowsel] <= 1'b0;
else
for (rowsel = 0; rowsel < DE; rowsel=rowsel+1)
d_data_out_en[rowsel] <= data_out_en[rowsel];
generate
for (i = 0; i < C_WIDTH; i=i+1) begin:gen_i
for (j = 0; j < WIDTH; j=j+1) begin:gen_j
assign clients_data_rotate[j][i] = clients_data_in_s[i][j];
end
end
endgenerate
generate
for (nw = 0; nw < WIDTH; nw=nw+1) begin : gen_nw
for (i = 0; i < DE; i=i+1) begin:gen_label
assign devices_data_rotate[nw][i] = |(clients_data_rotate[nw] & devices_one_hot_client_sel_s[i]);
end
end
endgenerate
generate
for (i = 0; i < WIDTH; i=i+1) begin:gen_i2
for (j = 0; j < DE; j=j+1) begin:gen_j2
assign devices_data_out_p[j][i] = devices_data_rotate[i][j];
end
end
endgenerate
always @*
begin
for (device = 0; device < DE; device = device + 1) begin
d_data_out_port[device*WIDTH+:WIDTH] = devices_data_out[device];
end
end
endmodule
regression_revised/issue_00287/issue_00287.ys 0 → 100644
tee -o result.out read_verilog -sv ../top.v
regression/scripts/issue_00300.ys → regression_revised/issue_00300/issue_00300.ys
......@@ -7,11 +7,9 @@ dump
write_ilang foo.ilang
memory_collect
stat
dump t:$mem
#dump t:$mem
design -reset
read_ilang foo.ilang
stat
memory_collect
dump t:$mem
write_verilog synth.v
tee -o result.out dump t:$mem
regression/scripts/issue_00306.ys → regression_revised/issue_00306/issue_00306.ys
......@@ -2,6 +2,3 @@ read_verilog ../top.v
proc
opt -full
synth -top top
write_verilog synth.v
regression/scripts/issue_00329.ys → regression_revised/issue_00329/issue_00329.ys
read_verilog -mem2reg ../top.v
write_verilog result.log
write_verilog result.out
regression/scripts/issue_00341.ys → regression_revised/issue_00341/issue_00341.ys
......@@ -4,7 +4,3 @@ equiv_make gold top_w equiv
opt -purge
equiv_simple
equiv_status -assert
design -reset
read_verilog ../top.v
synth
write_verilog synth.v
regression/issue_00342/top.v → regression_revised/issue_00342/top.v
......@@ -11,3 +11,11 @@ module top #(parameter AWIDTH=8,
always_latch
if (!cs_n && !r_wn) mem[addr] <= wdata;
endmodule
module generic_decoder
#(num_code_bits = 3,
localparam num_out_bits = 1 << num_code_bits)
(input [num_code_bits-1:0] A,
output reg [num_out_bits-1:0] Y);
endmodule
regression_revised/issue_00350/issue_00350.ys 0 → 100644
read_verilog -sv ../top.v
synth
abc -dff -g AND
opt
write_aiger -ascii -symbols <file.out>
design -reset
read_aiger <file.out>
write_verilog result.out
regression_revised/issue_00350/top.v 0 → 100644
module test
( input clk
, input in
, output out
);
reg [1:0] state = 0;
always @(posedge clk)
case (state)
0:
if (!in || in)
state <= 1;
else
state <= state;
1:
if (in)
state <= 1;
else
if (!in)
state <= 1;
else
state <= state;
endcase
always @(*)
case (state)
0:
out = 0;
1:
begin
if (in)
out = 1;
if (!in)
out = 0;
end
endcase
endmodule
regression/scripts/issue_00361.ys → regression_revised/issue_00361/issue_00361.ys
read_verilog -sv ../top.v
prep
alumacc
maccmap -unmap
synth -top top
write_verilog synth.v
select -assert-count 63 t:$add
select -assert-count 2 t:$macc
select -assert-count 65 t:$mul
regression_revised/issue_00362/issue_00362_fail.pat 0 → 100644
ERROR: Output port top.inst.b (inst) is connected to constants: 1'1
regression/scripts/issue_00291.ys → regression_revised/issue_00372/issue_00372.ys
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
select -assert-count 1 t:$_DFF_P_
regression/scripts/issue_00391.ys → regression_revised/issue_00391/issue_00391.ys
read_verilog -sv ../top.v
prep -top top -nordff
write_smt2 top.smt2
design -reset
read_verilog -sv ../top_clean.v
synth -top top
write_verilog synth.v
regression_revised/issue_00432/issue_00432.ys 0 → 100644
read_verilog -sv ../top.v
write_verilog result.v
design -reset
read_verilog result.v
hierarchy -check
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