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yosys-tests
Commit 40c3d62a by Miodrag Milanovic
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not possible to do write_firrtl after synth

parent 798a4221
Showing with 0 additions and 1 deletions
backends/scripts/write_firrtl.ys
......@@ -2,5 +2,4 @@ read_verilog ../top.v
proc
write_firrtl firrtl.firrtl
synth
write_firrtl firrtl2.firrtl
write_verilog synth.v
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