xilinx UG901 test. Divide to separate tests for each case.

Divided to understand regress on #171  build.

architecture/Makefile

@@ -80,7 +80,7 @@ $(eval $(call template,synth_xilinx_mux,synth_xilinx_mux))
 endif
 
 #xilinx_ug901_synthesis_examples
-$(eval $(call template,xilinx_ug901_synthesis_examples,xilinx_ug901_synthesis_examples))
+$(eval $(call template,xilinx_ug901_synthesis_examples, xilinx_ug901_asym_ram_sdp_read_wider xilinx_ug901_asym_ram_sdp_write_wider xilinx_ug901_asym_ram_tdp_read_first xilinx_ug901_asym_ram_tdp_write_first xilinx_ug901_black_box_1 xilinx_ug901_bytewrite_ram_1b xilinx_ug901_bytewrite_tdp_ram_nc xilinx_ug901_bytewrite_tdp_ram_readfirst2 xilinx_ug901_bytewrite_tdp_ram_rf xilinx_ug901_bytewrite_tdp_ram_wf xilinx_ug901_cmacc xilinx_ug901_cmult xilinx_ug901_dynamic_shift_registers_1 xilinx_ug901_dynpreaddmultadd xilinx_ug901_fsm_1 xilinx_ug901_latches xilinx_ug901_macc xilinx_ug901_mult_unsigned xilinx_ug901_presubmult xilinx_ug901_rams_dist xilinx_ug901_ram_simple_dual_one_clock xilinx_ug901_ram_simple_dual_two_clocks xilinx_ug901_rams_init_file xilinx_ug901_rams_pipeline xilinx_ug901_rams_sp_nc xilinx_ug901_rams_sp_rf xilinx_ug901_rams_sp_rf_rst xilinx_ug901_rams_sp_rom xilinx_ug901_rams_sp_rom_1 xilinx_ug901_rams_sp_wf xilinx_ug901_rams_tdp_rf_rf xilinx_ug901_registers_1 xilinx_ug901_sfir_shifter xilinx_ug901_shift_registers_0 xilinx_ug901_shift_registers_1 xilinx_ug901_squarediffmacc xilinx_ug901_top_mux xilinx_ug901_tristates_1 xilinx_ug901_tristates_2 xilinx_ug901_xilinx_ultraram_single_port_no_change xilinx_ug901_xilinx_ultraram_single_port_read_first xilinx_ug901_xilinx_ultraram_single_port_write_first))
 
 #greenpak4
 $(eval $(call template,synth_greenpak4,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))

architecture/run.sh

@@ -131,6 +131,8 @@ else
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/efinix/cells_sim.v
 	elif [ "$1" = "synth_efinix_fulladder" ]; then
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/efinix/cells_sim.v
+	elif [ "$1" = "xilinx_ug901_synthesis_examples" ]; then
+		:
 	else
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v
 	fi
@@ -139,14 +141,17 @@ else
 		touch .stamp
 		exit 0
 	fi
-
-	if ! vvp -N testbench > testbench.log 2>&1; then
-		grep 'ERROR' testbench.log
-		echo FAIL > ${1}_${2}.status
-	elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
-		echo FAIL > ${1}_${2}.status
-	else
+	if [ "$1" = "xilinx_ug901_synthesis_examples" ]; then
 		echo PASS > ${1}_${2}.status
+	else
+		if ! vvp -N testbench > testbench.log 2>&1; then
+			grep 'ERROR' testbench.log
+			echo FAIL > ${1}_${2}.status
+		elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
+			echo FAIL > ${1}_${2}.status
+		else
+			echo PASS > ${1}_${2}.status
+		fi
 	fi
 
 fi

architecture/scripts/xilinx_ug901_synthesis_examples.ys

-script ../run-test.sh

architecture/xilinx_ug901_synthesis_examples/.gitignore

-*.log

architecture/xilinx_ug901_synthesis_examples/run-test.sh

-#!/usr/bin/env bash
-set -e
-{
-echo "all::"
-for x in ../*.ys; do
-	echo "all:: run-$x"
-	echo "run-$x:"
-	echo "	@echo 'Running $x..'"
-	echo "	@yosys -ql ${x%.ys}.log $x"
-done
-} > run-test.mk
-exec ${MAKE:-make} -f run-test.mk