Reduce shift register length for less aggressive retiming

architecture/synth_xilinx_srl/test21.ys

@@ -6,4 +6,4 @@ write_verilog synth21.v
 
 # Check that retiming does not infer shift registers
 select t:SRL* -assert-count 0
-select t:FD* -assert-min 13
+select t:FD* -assert-min 20

architecture/synth_xilinx_srl/top.v

@@ -136,12 +136,12 @@ generate
     assign w1 = ^a[`N/2-1:0];
     shift_reg #(.depth(4)) sr0 (clk, w1, 1'b1, /*l*/, z[0], /* state */);
     assign w2 = ~^a[`N-1:`N/2];
-    shift_reg #(.depth(8), .neg_clk(1), .inferred(1), .init(1)) sr1 (clk, w2, r, /*l*/, z[1], /* state */);
+    shift_reg #(.depth(4), .neg_clk(1), .inferred(1), .init(1)) sr1 (clk, w2, r, /*l*/, z[1], /* state */);
     assign z[`N-1:2] = 'b0; // Suppress no driver warning
 `elsif TEST22
     wire w;
     assign w = ^a[`N-1:0];
-    shift_reg #(.depth(16), .inferred(1)) sr1 (clk, w, r, /*l*/, z[0], /* state */);
+    shift_reg #(.depth(8), .inferred(1)) sr1 (clk, w, r, /*l*/, z[0], /* state */);
     assign z[`N-1:1] = 'b0; // Suppress no driver warning
 `endif
 endgenerate