Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
Y
yosys-tests
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
yosys-tests
Commits
3a4a23f9
Commit
3a4a23f9
authored
Feb 14, 2020
by
Eddie Hung
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Add missing file for synth_xilinx_nowidelut
parent
331cad0e
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
7 additions
and
0 deletions
+7
-0
architecture/synth_xilinx/top_nowidelut.v
+7
-0
No files found.
architecture/synth_xilinx/top_nowidelut.v
0 → 100644
View file @
3a4a23f9
module
top
(
input
[
7
:
0
]
x
,
output
A
,
)
;
assign
A
=
^
x
;
endmodule
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment