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lvzhengyang
yosys-tests
Commits
3a4a23f9
Commit
3a4a23f9
authored
Feb 14, 2020
by
Eddie Hung
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Add missing file for synth_xilinx_nowidelut
parent
331cad0e
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architecture/synth_xilinx/top_nowidelut.v
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architecture/synth_xilinx/top_nowidelut.v
0 → 100644
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3a4a23f9
module
top
(
input
[
7
:
0
]
x
,
output
A
,
)
;
assign
A
=
^
x
;
endmodule
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