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yosys-tests
Commit 38626b9f by Miodrag Milanovic
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fixed splice test

parent 7d94b22e
Showing with 1 additions and 1 deletions
misc/scripts/splice_port.ys
read_verilog ../top.v read_verilog ../top.v
synth synth
splice -port data_a splice -port WR_EN
tee -o result.log dump tee -o result.log dump
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