improved values in tests

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_sdp_read_wider.ys

@@ -16,11 +16,7 @@ cd asym_ram_sdp_read_wider
 stat
 #Vivado synthesizes 1 RAMB18E1.
 select -assert-count 2 t:BUFG
-select -assert-count 271 t:FDRE
-select -assert-count 23 t:LUT2
-select -assert-count 194 t:LUT6
-select -assert-count 115 t:MUXF7
-select -assert-count 49 t:MUXF8
-select -assert-count 128 t:RAM64M
+select -assert-count 1 t:LUT2
+select -assert-count 4 t:RAMB18E1
 
-select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT6 115 t:MUXF7 49 t:MUXF8 128 t:RAM64M %% t:* %D
+select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_pipeline.ys

@@ -23,6 +23,6 @@ select -assert-count 2   t:BUFG
 #select -assert-count 21  t:LUT5
 #select -assert-count 356 t:LUT6
 #select -assert-count 2   t:MUXF7
-select -assert-count 256 t:RAM64M
+select -assert-count 2 t:RAMB18E1
 
-#select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:RAM128X1D %% t:* %D
+#select -assert-none t:BUFG t:FDRE t:RAMB18E1 %% t:* %D