Add bigsim/navre

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Makefile

-SUBDIRS = verific
+SUBDIRS = verific bigsim
 
 all: $(addsuffix /.stamp,$(SUBDIRS))
 	echo; find * -name "*.status" | sort | xargs grep -H . | sed 's,^,    ,; s,.status:,\t,; s,PASS,pass,;' | expand -t40; echo

bigsim/.gitignore

+/.stamp
+/*_cmos.status
+/*_ice40.status
+/*/work_sim
+/*/work_cmos
+/*/work_ice40
+/*/.stamp_sim
+/*/.stamp_cmos
+/*/.stamp_ice40

bigsim/Makefile

+all::
+	touch .stamp
+
+define template
+all:: $(addprefix $(1)/.stamp_,sim $(2))
+
+$(1)/.stamp_sim:
+	bash run.sh $(1) sim
+	touch $$@
+
+$(1)/.stamp_cmos: $(1)/.stamp_sim
+	bash run.sh $(1) cmos
+	touch $$@
+
+$(1)/.stamp_ice40: $(1)/.stamp_sim
+	bash run.sh $(1) ice40
+	touch $$@
+
+clean::
+	rm -rf $(1)/.stamp_* $(1)/work_*
+endef
+
+$(eval $(call template,navre,cmos ice40))
+
+.PHONY: all clean

bigsim/README.md

+Larger designs with test benches. We compare pre- and post-synthesis
+results for CMOS synthesis and iCE40.

bigsim/navre/README.md

+The Navré AVR clone (8-bit RISC)
+https://opencores.org/project/navre

bigsim/navre/config

+TOP="softusb_navre"
+RTL="softusb_navre.v"
+SIM="bench.v"

bigsim/navre/sim/bench.v

+
+module testbench;
+
+parameter pmem_width = 11;
+parameter dmem_width = 13;
+
+// navre inputs
+reg clk;
+reg rst;
+reg [15:0] pmem_d;
+reg [7:0] dmem_di;
+reg [7:0] io_di;
+reg [7:0] irq;
+
+// navre outputs
+wire pmem_ce;
+wire [pmem_width-1:0] pmem_a;
+wire dmem_we;
+wire [dmem_width-1:0] dmem_a;
+wire [7:0] dmem_do;
+wire io_re;
+wire io_we;
+wire [5:0] io_a;
+wire [7:0] io_do;
+wire [7:0] irq_ack;
+wire [pmem_width-1:0] dbg_pc;
+
+softusb_navre #(
+	pmem_width,
+	dmem_width
+) UUT (
+	clk,
+	rst,
+
+	pmem_ce,
+	pmem_a,
+	pmem_d,
+
+	dmem_we,
+	dmem_a,
+	dmem_di,
+	dmem_do,
+
+	io_re,
+	io_we,
+	io_a,
+	io_do,
+	io_di,
+
+	irq,
+	irq_ack,
+	dbg_pc
+);
+
+integer cycles;
+initial begin
+	clk <= 1;
+	rst <= 1;
+	cycles = 0;
+	while (cycles < 8) begin
+		#50; clk <= ~clk;
+		cycles = cycles + 1;
+		#50; clk <= ~clk;
+	end
+	rst <= #20 0;
+	forever begin
+		#50; clk <= ~clk;
+		cycles = cycles + 1;
+		#50; clk <= ~clk;
+		if (cycles == 10000) begin
+			$display("Reached limit of 10000 cpu cycles.");
+			$finish;
+		end
+	end
+end
+
+reg [15:0] addr;
+reg [15:0] pmem [2**pmem_width-1:0];
+reg [ 7:0] dmem [2**dmem_width-1:0];
+
+integer output_idx;
+reg [7:0] output_buf [1023:0];
+event output_eof;
+
+integer i;
+initial begin
+	for (i=0; i < 2**pmem_width; i = i+1) begin
+		pmem[i] = 0;
+	end
+	for (i=0; i < 2**dmem_width; i = i+1) begin
+		dmem[i] = 0;
+	end
+	`include "sieve.v"
+	output_idx = 0;
+end
+
+always @(posedge clk) begin
+	if (rst) begin
+		pmem_d <= 0;
+		irq <= 0;
+	end else if (pmem_ce) begin
+		addr = pmem_a * 2;
+		$display("+LOG+ %t PR @%x %x", $time, addr, pmem[pmem_a]);
+		pmem_d <= pmem[pmem_a];
+	end
+	if (dmem_we) begin
+		addr = dmem_a;
+		$display("+LOG+ %t DW @%x   %x", $time, addr, dmem_do);
+		dmem[dmem_a] <= dmem_do;
+	end
+	if (io_we && io_a == 42) begin
+		addr = io_a;
+		$display("+LOG+ %t IO @%x   %x  <---", $time, addr, io_do);
+		if (io_do == 0) begin
+			-> output_eof;
+		end else begin
+			output_buf[output_idx] = io_do;
+			output_idx = output_idx + 1;
+		end
+	end
+	dmem_di <= dmem[dmem_a];
+	io_di <= 0;
+end
+
+always @(output_eof) begin
+	#1001;
+	$display("Got EOF marker on IO port.");
+	for (i = 0; i < output_idx; i = i + 1) begin
+		$display("+OUT+ %t %d", $time, output_buf[i]);
+	end
+	$finish;
+end
+
+initial begin
+	// $dumpfile("bench.vcd");
+	// $dumpvars(0, testbench);
+end
+
+endmodule

bigsim/navre/sim/build.sh

+#!/bin/sh
+set -ex
+avr-gcc -Wall -Os -fno-inline -mmcu=avr2 -o sieve.elf sieve.c
+avr-objcopy -O ihex sieve.elf sieve.ihex
+python ihex2vlog.py < sieve.ihex > sieve.v
+avr-objdump -d sieve.elf
+rm -f sieve.elf sieve.ihex

bigsim/navre/sim/ihex2vlog.py

+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+import re
+
+ihex_pattern = re.compile(':([0-9a-fA-F]{2})([0-9a-fA-F]{4})([0-9a-fA-F]{2})([0-9a-fA-F]*)([0-9a-fA-F]{2})')
+
+while True:
+	m = ihex_pattern.match(raw_input())
+	if m:
+		count = int(m.group(1), 16)
+		address = int(m.group(2), 16)
+		rectype = int(m.group(3), 16)
+		data = [ int(m.group(4)[2*i:2*i+2], 16) for i in range(len(m.group(4))//2) ]
+		checksum = int(m.group(5), 16)
+		assert (checksum + count + address + address >> 8 + rectype + reduce(lambda x, y: x+y, data, 0)) & 0xff == 0
+		if rectype == 0x00:
+			for i in range(len(data)//2):
+				waddr = address//2 + i;
+				print("pmem[%4d] = 16'h%04x;" % (waddr, data[2*i] | data[2*i+1] << 8))
+		elif rectype == 0x01:
+			break
+		elif rectype == 0x03:
+			pass
+		else:
+			assert 0
+

bigsim/navre/sim/sieve.c

+// A simple Sieve of Eratosthenes
+
+#include <stdint.h>
+#include <stdbool.h>
+#ifndef AVR
+#  include <stdio.h>
+#else
+#  include <avr/io.h>
+#endif
+
+#define BITMAP_SIZE 24
+#define OUTPORT 42
+
+static uint8_t bitmap[BITMAP_SIZE/8];
+
+static void bitmap_set(uint8_t idx)
+{
+	bitmap[idx/8] |= 1 << (idx % 8);
+}
+
+static bool bitmap_get(uint8_t idx)
+{
+	return (bitmap[idx/8] & (1 << (idx % 8))) != 0;
+}
+
+static void output(uint8_t val)
+{
+#ifndef AVR
+	printf("%d\n",  val);
+#else
+	_SFR_IO8(OUTPORT) = val;
+#endif
+}
+
+int main()
+{
+	uint8_t i, j, k;
+	output(2);
+	for (i = 0; i < BITMAP_SIZE; i++) {
+		if (bitmap_get(i))
+			continue;
+		output(3+2*i);
+		for (j = 2*(3+2*i);; j += 3+2*i) {
+			if (j%2 == 0)
+				continue;
+			k = (j-3)/2;
+			if (k >= BITMAP_SIZE)
+				break;
+			bitmap_set(k);
+		}
+	}
+	output(0);
+	return 0;
+}
+

bigsim/navre/sim/sieve.v

+pmem[   0] = 16'hc00c;
+pmem[   1] = 16'hc01b;
+pmem[   2] = 16'hc01a;
+pmem[   3] = 16'hc019;
+pmem[   4] = 16'hc018;
+pmem[   5] = 16'hc017;
+pmem[   6] = 16'hc016;
+pmem[   7] = 16'hc015;
+pmem[   8] = 16'hc014;
+pmem[   9] = 16'hc013;
+pmem[  10] = 16'hc012;
+pmem[  11] = 16'hc011;
+pmem[  12] = 16'hc010;
+pmem[  13] = 16'h2411;
+pmem[  14] = 16'hbe1f;
+pmem[  15] = 16'he5cf;
+pmem[  16] = 16'he0d2;
+pmem[  17] = 16'hbfde;
+pmem[  18] = 16'hbfcd;
+pmem[  19] = 16'he010;
+pmem[  20] = 16'he6a0;
+pmem[  21] = 16'he0b0;
+pmem[  22] = 16'hc001;
+pmem[  23] = 16'h921d;
+pmem[  24] = 16'h36a3;
+pmem[  25] = 16'h07b1;
+pmem[  26] = 16'hf7e1;
+pmem[  27] = 16'hd028;
+pmem[  28] = 16'hc059;
+pmem[  29] = 16'hcfe2;
+pmem[  30] = 16'h2fe8;
+pmem[  31] = 16'h95e6;
+pmem[  32] = 16'h95e6;
+pmem[  33] = 16'h95e6;
+pmem[  34] = 16'he0f0;
+pmem[  35] = 16'h5ae0;
+pmem[  36] = 16'h4fff;
+pmem[  37] = 16'h7087;
+pmem[  38] = 16'he021;
+pmem[  39] = 16'he030;
+pmem[  40] = 16'hc001;
+pmem[  41] = 16'h0f22;
+pmem[  42] = 16'h958a;
+pmem[  43] = 16'hf7ea;
+pmem[  44] = 16'h8180;
+pmem[  45] = 16'h2b82;
+pmem[  46] = 16'h8380;
+pmem[  47] = 16'h9508;
+pmem[  48] = 16'h2fe8;
+pmem[  49] = 16'h95e6;
+pmem[  50] = 16'h95e6;
+pmem[  51] = 16'h95e6;
+pmem[  52] = 16'he0f0;
+pmem[  53] = 16'h5ae0;
+pmem[  54] = 16'h4fff;
+pmem[  55] = 16'h8120;
+pmem[  56] = 16'he030;
+pmem[  57] = 16'h7087;
+pmem[  58] = 16'hc002;
+pmem[  59] = 16'h9535;
+pmem[  60] = 16'h9527;
+pmem[  61] = 16'h958a;
+pmem[  62] = 16'hf7e2;
+pmem[  63] = 16'h2f82;
+pmem[  64] = 16'h7081;
+pmem[  65] = 16'h9508;
+pmem[  66] = 16'hbd8a;
+pmem[  67] = 16'h9508;
+pmem[  68] = 16'h931f;
+pmem[  69] = 16'h93cf;
+pmem[  70] = 16'h93df;
+pmem[  71] = 16'he082;
+pmem[  72] = 16'hdff9;
+pmem[  73] = 16'he0c3;
+pmem[  74] = 16'he0d0;
+pmem[  75] = 16'h2f8d;
+pmem[  76] = 16'hdfe3;
+pmem[  77] = 16'h1181;
+pmem[  78] = 16'hc01b;
+pmem[  79] = 16'h2f8c;
+pmem[  80] = 16'hdff1;
+pmem[  81] = 16'h2f1c;
+pmem[  82] = 16'h0f11;
+pmem[  83] = 16'hff10;
+pmem[  84] = 16'hc013;
+pmem[  85] = 16'h2f41;
+pmem[  86] = 16'he050;
+pmem[  87] = 16'h2f24;
+pmem[  88] = 16'h2f35;
+pmem[  89] = 16'h5023;
+pmem[  90] = 16'h0931;
+pmem[  91] = 16'hff37;
+pmem[  92] = 16'hc004;
+pmem[  93] = 16'h2f24;
+pmem[  94] = 16'h2f35;
+pmem[  95] = 16'h5022;
+pmem[  96] = 16'h0931;
+pmem[  97] = 16'h2f82;
+pmem[  98] = 16'h2f93;
+pmem[  99] = 16'h9595;
+pmem[ 100] = 16'h9587;
+pmem[ 101] = 16'h3188;
+pmem[ 102] = 16'hf418;
+pmem[ 103] = 16'hdfb6;
+pmem[ 104] = 16'h0f1c;
+pmem[ 105] = 16'hcfe9;
+pmem[ 106] = 16'h5fdf;
+pmem[ 107] = 16'h5fce;
+pmem[ 108] = 16'h31d8;
+pmem[ 109] = 16'hf6e9;
+pmem[ 110] = 16'he080;
+pmem[ 111] = 16'hdfd2;
+pmem[ 112] = 16'he080;
+pmem[ 113] = 16'he090;
+pmem[ 114] = 16'h91df;
+pmem[ 115] = 16'h91cf;
+pmem[ 116] = 16'h911f;
+pmem[ 117] = 16'h9508;
+pmem[ 118] = 16'h94f8;
+pmem[ 119] = 16'hcfff;

bigsim/run.sh

+#!/bin/bash
+
+set -ex
+source $1/config
+mkdir $1/work_$2
+cd $1/work_$2
+
+iverilog_cmd="iverilog -o sim -s testbench -I../rtl -I../sim"
+
+rtl_files=""
+for fn in $RTL; do
+	rtl_files="$rtl_files ../rtl/$fn"
+done
+
+case "$2" in
+	sim)
+		iverilog_cmd="$iverilog_cmd $rtl_files"
+		;;
+	cmos)
+		yosys -ql synthlog.txt -p "synth -top $TOP; abc -g cmos4; write_verilog synth.v" $rtl_files
+		iverilog_cmd="$iverilog_cmd synth.v"
+		;;
+	ice40)
+		yosys -ql synthlog.txt -p "synth_ice40 -top $TOP; write_verilog synth.v" $rtl_files
+		iverilog_cmd="$iverilog_cmd synth.v $(yosys-config --datdir/ice40/cells_sim.v)"
+		;;
+	*)
+		exit 1
+		;;
+esac
+
+for fn in $SIM; do
+	iverilog_cmd="$iverilog_cmd ../sim/$fn"
+done
+$iverilog_cmd
+
+vvp -N sim | pv -l > output.txt
+
+if [ "$2" != "sim" ]; then
+	if cmp output.txt ../work_sim/output.txt; then
+		echo pass > ../../${1}_${2}.status
+	else
+		echo fail > ../../${1}_${2}.status
+	fi
+fi

verific/README.md

+Test cases for Yosys+Verific (mostly using SymbiYosys)