Commit 2eae2bac by Eddie Hung

Check that resets block SRLs

parent 6d4b3907
......@@ -263,3 +263,5 @@ cd $paramod\template\inferred=1\init=1\neg_clk=1\len=127; select t:FD* -assert-c
cd $paramod\template\inferred=1\init=1\neg_clk=1\len=128; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\template\inferred=1\init=1\neg_clk=1\len=129; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\template\inferred=1\init=1\neg_clk=1\len=130; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\template\len=131\er_is_reset=1; select t:SRL* -assert-count 0
cd $paramod\template\inferred=1\init=1\neg_clk=1\len=131\er_is_reset=1; select t:SRL* -assert-count 0
`include "defines.vh"
module template(input clk, input a, input e, output z);
module template(input clk, input a, input er, output z);
parameter inferred = 0;
parameter init = 0;
parameter neg_clk = 0;
parameter len = 1;
parameter er_is_reset = 0;
generate
if (inferred == 0) begin
wire [len:0] int;
......@@ -12,9 +13,15 @@ generate
genvar i;
for (i = 0; i < len; i=i+1) begin
if (neg_clk)
\$_DFFE_NP_ r(.C(clk), .D(int[i]), .E(e), .Q(int[i+1]));
if (!er_is_reset)
\$_DFFE_NP_ r(.C(clk), .D(int[i]), .E(er), .Q(int[i+1]));
else
\$_DFFE_PP_ r(.C(clk), .D(int[i]), .E(e), .Q(int[i+1]));
\$_DFF_NP0_ r(.C(clk), .D(int[i]), .R(er), .Q(int[i+1]));
else
if (!er_is_reset)
\$_DFFE_PP_ r(.C(clk), .D(int[i]), .E(er), .Q(int[i+1]));
else
\$_DFF_PP0_ r(.C(clk), .D(int[i]), .R(er), .Q(int[i+1]));
end
assign z = int[len];
end
......@@ -29,19 +36,39 @@ generate
if (len == 1) begin
if (neg_clk) begin
always @(negedge clk) if (e) int <= a;
if (!er_is_reset) begin
always @(negedge clk) if (er) int <= a;
end
else begin
always @(negedge clk or posedge er) if (er) int <= 1'b0; else int <= a;
end
end
else begin
if (!er_is_reset) begin
always @(posedge clk) if (er) int <= a;
end
else begin
always @(posedge clk) if (e) int <= a;
always @(posedge clk or posedge er) if (er) int <= 1'b0; else int <= a;
end
end
assign z = int;
end
else begin
if (neg_clk) begin
always @(negedge clk) if (e) int <= { int[len-2:0], a };
if (!er_is_reset) begin
always @(negedge clk) if (er) int <= { int[len-2:0], a };
end
else begin
always @(posedge clk) if (e) int <= { int[len-2:0], a };
always @(negedge clk or posedge er) if (er) int <= 'b0; else int <= { int[len-2:0], a };
end
end
else begin
if (!er_is_reset) begin
always @(posedge clk) if (er) int <= { int[len-2:0], a };
end
else begin
always @(posedge clk or posedge er) if (er) int <= 'b0; else int <= { int[len-2:0], a };
end
end
assign z = int[len-1];
end
......@@ -49,7 +76,7 @@ generate
endgenerate
endmodule
module top(input clk, input [`N-1:0] a, input e, output [`N-1:0] z1, z2, z3, z4, z5, z6);
module top(input clk, input [`N-1:0] a, input e, r, output [`N-1:0] z1, z2, z3, z4, z5, z6, z7, z8);
generate
genvar i;
for (i = 0; i < `N; i=i+1) begin : pos_clk_no_enable_no_init_not_inferred
......@@ -70,5 +97,11 @@ generate
for (i = 0; i < `N; i=i+1) begin : neg_clk_with_enable_with_init_inferred
template #(.len(i+1), .neg_clk(1), .inferred(1), .init(1)) sr(clk, a[i], e, z6[i]);
end
// Check that use of resets block shreg
(* keep *)
template #(.len(`N), .er_is_reset(1)) pos_clk_no_enable_no_init_not_inferred_with_reset(clk, a[`N-1], r, z7[`N-1]);
(* keep *)
template #(.len(`N), .neg_clk(1), .inferred(1), .init(1), .er_is_reset(1)) neg_clk_no_enable_with_init_with_inferred_with_reset(clk, a[`N-1], r, z8[`N-1]);
endgenerate
endmodule
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