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lvzhengyang
yosys-tests
Commits
2c633693
Commit
2c633693
authored
Oct 07, 2019
by
SergeyDegtyar
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Fix regressions on build #179
parent
58aa1c9e
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architecture/run.sh
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architecture/run.sh
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2c633693
...
...
@@ -100,9 +100,9 @@ else
elif
[
"
$1
"
=
"synth_ice40_fulladder"
]
;
then
iverilog
-o
testbench ../testbench.v synth.v ../../common.v
$COMMON_PREFIX
/simcells.v
$TECHLIBS_PREFIX
/ice40/cells_sim.v
elif
[
"
$1
"
=
"ice40_wrapcarry"
]
;
then
iverilog
-o
testbench ../testbench.v synth.v ../../common.v
$COMMON_PREFIX
/simcells.v
$TECHLIBS_PREFIX
/ice40/cells_sim.v
iverilog
-o
testbench ../testbench.v synth.v ../../common.v
$COMMON_PREFIX
/simcells.v
$TECHLIBS_PREFIX
/ice40/cells_sim.v
$TECHLIBS_PREFIX
/ice40/abc_model.v
elif
[
"
$1
"
=
"ice40_wrapcarry_adders"
]
;
then
iverilog
-o
testbench ../testbench.v synth.v ../../common.v
$COMMON_PREFIX
/simcells.v
$TECHLIBS_PREFIX
/ice40/cells_sim.v
iverilog
-o
testbench ../testbench.v synth.v ../../common.v
$COMMON_PREFIX
/simcells.v
$TECHLIBS_PREFIX
/ice40/cells_sim.v
$TECHLIBS_PREFIX
/ice40/abc_model.v
elif
[
"
$1
"
=
"synth_intel"
]
;
then
iverilog
-o
testbench ../testbench.v synth.v ../../common.v
$COMMON_PREFIX
/simcells.v
$TECHLIBS_PREFIX
/intel/max10/cells_sim.v
elif
[
"
$1
"
=
"synth_intel_a10gx"
]
;
then
...
...
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