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yosys-tests
Commit 1e5bb203 by Eddie Hung
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Fix tests

parent f0c85bdb
Showing with 3 additions and 3 deletions
architecture/synth_xilinx_srl/test10.ys
......@@ -139,7 +139,7 @@ cd synth; cd pos_clk_no_enable_no_init_not_inferred_var_len[124].sr; select t:FD
cd synth; cd pos_clk_no_enable_no_init_not_inferred_var_len[125].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
cd synth; cd pos_clk_no_enable_no_init_not_inferred_var_len[126].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
cd synth; cd pos_clk_no_enable_no_init_not_inferred_var_len[127].sr; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_no_enable_no_init_not_inferred_var_len[127].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_no_enable_no_init_not_inferred_var_len[128].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_no_enable_no_init_not_inferred_var_len[129].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_no_enable_no_init_not_inferred_var_len[130].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test11.ys
......@@ -139,7 +139,7 @@ cd synth; cd neg_clk_with_enable_with_init_inferred_var_len[124].sr; select t:FD
cd synth; cd neg_clk_with_enable_with_init_inferred_var_len[125].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred_var_len[126].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred_var_len[127].sr; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred_var_len[127].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred_var_len[128].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred_var_len[129].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred_var_len[130].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test15.ys
......@@ -2,7 +2,7 @@ read_verilog -icells -DTEST15 ../top.v
synth_xilinx
rename -top synth
clean -purge
write_verilog -noexpr -norename synth15.v
write_verilog synth15.v
cd synth; cd pos_clk_no_enable_no_init_not_inferred_long[0].sr; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd pos_clk_no_enable_no_init_not_inferred_long[1].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
......
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