Add some new testcases

architecture/synth_xilinx_dsp/macc_25s_18s__49bitaccum.v

+(* top *)
+module macc_25s_18s__49bitaccum #(parameter AW=25, BW=18, AREG=0, BREG=0, MREG=0) (input clk, CEA, CEB, CEM, CEP, input signed [AW-1:0] A, input signed [BW-1:0] B, output reg signed [49-1:0] P);
+reg signed [AW-1:0] Ar;
+reg signed [BW-1:0] Br;
+reg signed [AW+BW-1:0] Mr;
+generate
+    if (AREG) begin
+        always @(posedge clk) if (1) Ar <= A;
+    end
+    else
+        always @* Ar <= A;
+    if (BREG) begin
+        always @(posedge clk) if (1) Br <= B;
+    end
+    else
+        always @* Br <= B;
+    if (MREG) begin
+        always @(posedge clk) if (1) Mr <= Ar * Br;
+    end
+    else
+        always @* Mr <= Ar * Br;
+    always @(posedge clk) if (1) P <= P + Mr;
+endgenerate
+endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd macc_25s_18s__49bitaccum; select t:DSP48E1 -assert-count 1; select t:FD* -assert-count 49; select t:XORCY -assert-count 49; select t:LUT2 -assert-count 97";
+endmodule
+`endif
+

architecture/synth_xilinx_dsp/ug901a.v

+// Signed 40-bit streaming accumulator with 16-bit inputs
+// File: HDL_Coding_Techniques/multipliers/multipliers4.v
+//
+// Source:
+// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf p.90
+//
+(* top *)
+module ug901a # (parameter SIZEIN = 16, SIZEOUT = 40) (
+	input clk, ce, sload,
+	input signed [SIZEIN-1:0] a, b,
+	output signed [SIZEOUT-1:0] accum_out
+);
+// Declare registers for intermediate values
+reg signed [SIZEIN-1:0] a_reg, b_reg;
+reg sload_reg;
+reg signed [2*SIZEIN-1:0] mult_reg;
+reg signed [SIZEOUT-1:0] adder_out, old_result;
+always @* /*(adder_out or sload_reg)*/ begin // Modification necessary to fix sim/synth mismatch
+	if (sload_reg)
+		old_result <= 0;
+	else
+		// 'sload' is now active (=low) and opens the accumulation loop.
+		// The accumulator takes the next multiplier output in
+		// the same cycle.
+		old_result <= adder_out;
+end
+
+always @(posedge clk)
+	if (ce)
+	begin
+		a_reg <= a;
+		b_reg <= b;
+		mult_reg <= a_reg * b_reg;
+		sload_reg <= sload;
+		// Store accumulation result into a register
+		adder_out <= old_result + mult_reg;
+	end
+
+	// Output accumulation result
+	assign accum_out = adder_out;
+
+	endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd ug901a; select t:DSP48E1 -assert-count 1; select t:FDRE -assert-count 1; select -assert-none t:DSP48E1 t:BUFG t:FDRE %% t:* %D";
+endmodule
+`endif
+

architecture/synth_xilinx_dsp/ug901b.v

+// 8-Tap Even Symmetric Systolic FIR
+//
+// Source:
+// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf p.93
+//
+(* top *)
+module ug901b #(parameter nbtap = 4, dsize = 16, psize = 2*dsize) (
+input clk, 
+input signed [dsize-1:0] datain, 
+output signed [2*dsize-1:0] firout
+);
+wire signed [dsize-1:0] h [nbtap-1:0];
+wire signed [dsize-1:0] arraydata [nbtap-1:0];
+wire signed [psize-1:0] arrayprod [nbtap-1:0];
+wire signed [dsize-1:0] shifterout;
+reg signed [dsize-1:0] dataz [nbtap-1:0];
+
+assign h[0] = 7;
+assign h[1] = 14;
+assign h[2] = -138;
+assign h[3] = 129;
+
+assign firout = arrayprod[nbtap-1]; // Connect last product to output
+
+sfir_shifter #(dsize, nbtap) shifter_inst0 (
+	clk,
+	datain,
+	shifterout);
+
+generate
+	genvar I;
+	for (I=0; I<nbtap; I=I+1)
+		if (I==0)
+			sfir_even_symmetric_systolic_element #(dsize) fte_inst0 (
+				clk,
+				h[I],
+                datain,
+                shifterout,
+                {32{1'b0}},
+                arraydata[I],
+				arrayprod[I]);
+		else
+			sfir_even_symmetric_systolic_element #(dsize) fte_inst (
+                clk,
+                h[I],
+                arraydata[I-1],
+                shifterout,
+                arrayprod[I-1],
+                arraydata[I],
+                arrayprod[I]);
+	endgenerate
+endmodule
+
+(* dont_touch = "yes" *)
+module sfir_shifter #(parameter dsize = 16, nbtap = 4) (
+     input clk, 
+     input [dsize-1:0] datain, 
+     output [dsize-1:0] dataout
+);
+(* srl_style = "srl_register" *) reg [dsize-1:0] tmp [0:2*nbtap-1];
+integer i;
+always @(posedge clk)
+begin
+    tmp[0] <= datain;
+    for (i=0; i<=2*nbtap-2; i=i+1)
+        tmp[i+1] <= tmp[i];
+end
+assign dataout = tmp[2*nbtap-1];
+endmodule
+
+module sfir_even_symmetric_systolic_element #(parameter dsize = 16) (
+    input clk, 
+    input signed [dsize-1:0] coeffin, datain, datazin,
+    input signed [2*dsize-1:0] cascin,
+    output signed [dsize-1:0] cascdata,
+    output reg signed [2*dsize-1:0] cascout
+);
+reg signed [dsize-1:0] coeff;
+reg signed [dsize-1:0] data;
+reg signed [dsize-1:0] dataz;
+reg signed [dsize-1:0] datatwo;
+reg signed [dsize:0] preadd;
+reg signed [2*dsize-1:0] product;
+assign cascdata = datatwo;
+
+always @(posedge clk)
+begin
+    coeff <= coeffin;
+    data <= datain;
+    datatwo <= data;
+    dataz <= datazin;
+    preadd <= datatwo + dataz;
+    product <= preadd * coeff;
+    cascout <= product + cascin;
+end
+
+endmodule
+
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd ug901b; select t:DSP48E1 -assert-count 1; select t:FDRE -assert-count 1; select -assert-none t:DSP48E1 t:BUFG t:FDRE %% t:* %D";
+endmodule
+`endif
+