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yosys-tests
Unverified Commit 14c4bf6f by Miodrag Milanović Committed by GitHub
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Merge pull request #38 from SergeyDegtyar/master 

Add tests for error messages to 'simple' group
parents 14623819 e9244062
Showing with 2541 additions and 3 deletions
simple/Makefile
......@@ -17,6 +17,19 @@ clean::
))
endef
define template_error
$(foreach design,$(1),
$(foreach script,$(2),
work:: $(design)/work_$(script)/.stamp
$(design)/work_$(script)/.stamp:
bash run.sh $(design) $(script)
clean::
rm -rf $(design)/work_$(script)
))
endef
$(eval $(call template,alu,gates luts))
# DFF with constant drivers
......@@ -59,9 +72,11 @@ $(eval $(call template,reduce,reduce reduce_allow_off_chain))
#nlutmap
$(eval $(call template,nlutmap,nlutmap))
$(eval $(call template,nlutmap_opt,nlutmap_luts nlutmap_assert))
$(eval $(call template_error,nlutmap_error,nlutmap_error))
#zinit
$(eval $(call template,zinit,zinit zinit_singleton))
$(eval $(call template_error,zinit_error,zinit_failed_to_handle))
#clk2fflogic (104 - 144,180-195 is not reached)
$(eval $(call template,clk2fflogic,clk2fflogic))
......@@ -77,6 +92,7 @@ $(eval $(call template,aigmap,aigmap aigmap_nand))
#memory_memx, memory_nordff(75-101 not covered), memory_unpack(91-108 not covered)
$(eval $(call template,memory,memory memory_memx memory_nordff memory_unpack memory_nomap memory_nordff_opt memory_memx_opt memory_bram_opt memory_share))
$(eval $(call template_error,memory_bram_error, memory_bram_syntax_error_in_rules memory_bram_cant_open_rules_file ))
#uniquify
$(eval $(call template,uniquify,uniquify))
......@@ -84,6 +100,7 @@ $(eval $(call template,uniquify,uniquify))
#hierarchy (44% increased to 61,3%)
$(eval $(call template,hierarchy,hierarchy hierarchy_top hierarchy_check hierarchy_simcheck hierarchy_purge_lib hierarchy_libdir hierarchy_keep_positionals hierarchy_keep_portwidths hierarchy_nokeep_asserts hierarchy_auto_top hierarchy_generate))
$(eval $(call template,hierarchy_huge,hierarchy_huge))
$(eval $(call template_error,hierarchy_error, hierarchy_no_top_module hierarchy_top_requires_args hierarchy_module_not_found ))
#attrmap
$(eval $(call template,attrmap,attrmap attrmap_modattr))
......@@ -91,6 +108,7 @@ $(eval $(call template,attrmap,attrmap attrmap_modattr))
#dff2dffe -unmap
# dff2dffe_unmap_direct - skipped: ERROR: Found error in internal cell \dffe.$procdff$47 ($dffe) at
$(eval $(call template,dff2dffe_unmap,dff2dffe_unmap dff2dffe_unmap_mince dff2dffe_unmap_direct))
$(eval $(call template_error,dff2dffe_error,dff2dffe_error))
#dff2dffs
$(eval $(call template,dff2dffs,dff2dffs))
......@@ -100,14 +118,17 @@ $(eval $(call template,dffsr2dff,dffsr2dff))
#extract
$(eval $(call template,extract,extract_cell_attr extract_compat extract_constports extract_map_design extract_ignore_parameters extract_ignore_param extract_map extract_mine_cells_span extract_mine_limit_matches_per_module extract_mine_max_fanout extract_mine_min_freq extract_mine_split extract_mine extract_nodefaultswaps extract_perm extract_swap extract_verbose extract_wire_attr ))
$(eval $(call template_error,extract_error, extract_mine_and_map extract_map_and_mine extract_args_to_perm extract_missing_opt extract_cant_open_map_file extract_cant_open_output ))
#extract_counter
$(eval $(call template,extract_counter,extract_counter extract_counter_maxwidth extract_counter_pout))
$(eval $(call template,extract_counter_down,extract_counter extract_counter_maxwidth extract_counter_pout))
$(eval $(call template_error,extract_counter_error,extract_counter_pout_without_args))
#shregmap
$(eval $(call template,shregmap,shregmap shregmap_clkpol_any shregmap_clkpol_neg shregmap_clkpol_pos shregmap_enpol_any shregmap_enpol_any_or_none shregmap_enpol_neg shregmap_enpol_none shregmap_enpol_pos shregmap_init shregmap_keep_after shregmap_keep_before shregmap_match shregmap_maxlen shregmap_minlen shregmap_params shregmap_tech shregmap_zinit))
$(eval $(call template,shregmap_resetable,shregmap shregmap_clkpol_any shregmap_clkpol_neg shregmap_clkpol_pos shregmap_enpol_any shregmap_enpol_any_or_none shregmap_enpol_neg shregmap_enpol_none shregmap_enpol_pos shregmap_init shregmap_keep_after shregmap_keep_before shregmap_match shregmap_maxlen shregmap_minlen shregmap_params shregmap_tech shregmap_zinit))
$(eval $(call template_error,shregmap_error,shregmap_zinit_init shregmap_match_clkpol shregmap_match_enpol shregmap_match_params))
#design_import
$(eval $(call template,design_import, design_import design_import_as ))
......@@ -140,9 +161,11 @@ $(eval $(call template,fsm_expand, fsm_expand fsm_expand_full))
#fsm_export
$(eval $(call template,fsm_export, fsm_export fsm_export_noauto fsm_export_o fsm_export_origenc))
$(eval $(call template_error,fsm_export_error, fsm_export_couldnt_open_file))
#fsm_recode
$(eval $(call template,fsm_recode, fsm_recode fsm_recode_encoding_binary fsm_recode_encoding_binary_twice fsm_recode_encoding_one_hot fsm_recode_fm_set_fsm_file fsm_recode_all_opt))
$(eval $(call template_error,fsm_recode_error, fsm_recode_encoding_isnt_supported fsm_recode_cant_open_fm_set_fsm_file fsm_recode_cant_open_encfile ))
#fsm command
$(eval $(call template,fsm_command, fsm_command fsm_fm_set_fsm_file fsm_encfile fsm_encoding_binary fsm_encoding_one-hot fsm_encoding_auto fsm_encoding_none fsm_encoding_user fsm_encoding_unknown fsm_nodetect fsm_norecode fsm_nomap fsm_command_expand fsm_fullexpand fsm_command_export ))
......@@ -192,11 +215,15 @@ $(eval $(call template,proc_arst_reduce, proc_arst proc_arst_global_rst proc_ar
#submod
$(eval $(call template, submod, submod submod_top submod_copy submod_name submod_no_proc submod_no_hier))
$(eval $(call template, submod_mem, submod submod_top submod_copy submod_name submod_no_proc submod_no_hier submod_mem))
$(eval $(call template_error, submod_error, submod_error))
#prep
$(eval $(call template, prep, prep prep_top prep_auto_top prep_flatten prep_ifx prep_memx prep_nomem prep_nordff prep_rdff prep_nokeepdc prep_run prep_run_begin))
$(eval $(call template_error, prep_error, prep_error))
#synth
$(eval $(call template, synth, synth synth_top synth_auto_top synth_encfile synth_run synth_run_full synth_flatten synth_lut synth_nofsm synth_noabc synth_noabc_lut synth_noalumacc synth_nordff synth_noshare))
$(eval $(call template_error, synth_error, synth_error))
.PHONY: all clean
simple/dff2dffe_error/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
simple/dff2dffe_error/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple/extract_counter_error/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg rst;
wire [7:0] f;
top uut ( .clk(clk),
.reset(rst),
.out(f));
initial begin
rst <= 1;
#5
rst <= 0;
end
assert_expr f_test(.clk(clk), .A(f[0]));
endmodule
module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A === 1'bX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
simple/extract_counter_error/top.v 0 → 100644
module top (
out,
clk,
reset
);
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
if (reset) begin
out <= 8'b0 ;
end else
`ifndef BUG
out <= out + 1;
`else
out <= out - 1'bZ;
`endif
//FORCE
endmodule
simple/extract_error/out 0 → 100644
# Generated by Yosys 0.8+492 (git sha1 2058c7c5, gcc 8.3.0-6ubuntu1~18.10 -Og -fPIC)
autoidx 1
simple/extract_error/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk)
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk)
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk)
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
simple/extract_error/top.ilang 0 → 100644
# Generated by Yosys 0.8+492 (git sha1 2058c7c5, gcc 8.3.0-6ubuntu1~18.10 -Og -fPIC)
autoidx 143
simple/extract_error/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk)
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple/fsm_export_error/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
function [31:0] xorshift32;
input [31:0] arg;
begin
xorshift32 = arg;
// Xorshift32 RNG, doi:10.18637/jss.v008.i14
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
reg [31:0] rng = 123456789;
always @(posedge clk) rng <= xorshift32(rng);
wire a = xorshift32(rng * 5);
wire b = xorshift32(rng * 7);
reg rst;
wire g0;
wire g1;
top uut (
.a (a),
.b (b),
.clk (clk),
.rst (rst),
.g0(g0),
.g1(g1)
);
initial begin
rst <= 1;
#5
rst <= 0;
end
assert_Z g0_test(.clk(clk), .A(g0));
assert_Z g1_test(.clk(clk), .A(g1));
endmodule
simple/fsm_export_error/top.v 0 → 100644
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock,reset,req_0,req_1;
output gnt_0,gnt_1;
wire clock,reset,req_0,req_1;
reg gnt_0,gnt_1;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case(state)
IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0;
`ifndef BUG
gnt_0 <= 1;
`else
gnt_0 <= 1'bZ;
`endif
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2 : if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default : state <= #1 IDLE;
endcase
end
endmodule
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
fsm u_fsm ( .clock(clk),
.reset(rst),
.req_0(a),
.req_1(b),
.gnt_0(g0),
.gnt_1(g1));
endmodule
simple/fsm_recode_error/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
function [31:0] xorshift32;
input [31:0] arg;
begin
xorshift32 = arg;
// Xorshift32 RNG, doi:10.18637/jss.v008.i14
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
reg [31:0] rng = 123456789;
always @(posedge clk) rng <= xorshift32(rng);
wire a = xorshift32(rng * 5);
wire b = xorshift32(rng * 7);
reg rst;
wire g0;
wire g1;
top uut (
.a (a),
.b (b),
.clk (clk),
.rst (rst),
.g0(g0),
.g1(g1)
);
initial begin
rst <= 1;
#5
rst <= 0;
end
assert_Z g0_test(.clk(clk), .A(g0));
assert_Z g1_test(.clk(clk), .A(g1));
endmodule
simple/fsm_recode_error/top.v 0 → 100644
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock,reset,req_0,req_1;
output gnt_0,gnt_1;
wire clock,reset,req_0,req_1;
reg gnt_0,gnt_1;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case(state)
IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0;
`ifndef BUG
gnt_0 <= 1;
`else
gnt_0 <= 1'bZ;
`endif
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2 : if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default : state <= #1 IDLE;
endcase
end
endmodule
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
fsm u_fsm ( .clock(clk),
.reset(rst),
.req_0(a),
.req_1(b),
.gnt_0(g0),
.gnt_1(g1));
endmodule
simple/hierarchy_error/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
simple/hierarchy_error/top.v 0 → 100644
module dff
( input d, clk, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
q <= d;
endmodule
module adff
( inout d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
parameter S=0;
initial begin
q = 1'bX;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
parameter Z=1'bZ;
initial begin
q = Z;
end
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( d, clk, pre, clr, q );
parameter s=2;
parameter l=1;
input [s-1:l] d;
input clk, pre, clr;
output reg [s-1:l] q;
initial begin
q = 2'b11;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 2'b00;
`else
q <= d;
`endif
else if ( !pre )
q <= 2'b11;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
wire a1,b11;
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr #(4) u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d ({a,a1} ),
.q ({b1,b11} )
);
defparam u_ndffnsnr.l = 0;
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple/memory_bram_error/rules.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
`ifndef BUG
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
`else
if (we_a)
begin
ram[addr_a] <= 8'bXXXXXXXX;
q_a <= 8'bXXXXXXXX;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
`endif
end
// Port B
always @ (posedge clk)
begin
`ifndef BUG
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
`else
if (we_b)
begin
ram[addr_b] <= 8'bXXXXXXXX;
q_b <= 8'bXXXXXXXX;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
`endif
end
endmodule
simple/memory_bram_error/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [7:0] data_b = 0;
reg [5:0] addr_a = 0;
reg [5:0] addr_b = 0;
reg we_a = 0;
reg we_b = 1;
reg re_a = 1;
reg re_b = 1;
wire [7:0] q_a,q_b;
reg mem_init = 0;
top uut (
.data_a(data_a),
.data_b(data_b),
.addr_a(addr_a),
.addr_b(addr_b),
.we_a(we_a),
.we_b(we_b),
.re_a(re_a),
.re_b(re_b),
.clk(clk),
.q_a(q_a),
.q_b(q_b)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
data_b <= data_b + 5;
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
we_b <= !we_b;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
simple/memory_bram_error/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
`ifndef BUG
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
`else
if (we_a)
begin
ram[addr_a] <= 8'bXXXXXXXX;
q_a <= 8'bXXXXXXXX;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
`endif
end
// Port B
always @ (posedge clk)
begin
`ifndef BUG
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
`else
if (we_b)
begin
ram[addr_b] <= 8'bXXXXXXXX;
q_b <= 8'bXXXXXXXX;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
`endif
end
endmodule
simple/nlutmap_error/testbench.v 0 → 100644
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
simple/nlutmap_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
wire p,r,s;
xor (p,x,y);
`ifndef BUG
xor (A,p,cin);
`else
and (A,p,cin);
`endif
and(r,p,cin);
and(s,x,y);
or(cout,r,s);
endmodule
simple/prep_error/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
simple/prep_error/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple/scripts/dff2dffe_error.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe -direct-match $ff
simple/scripts/extract_args_to_perm.ys 0 → 100644
read_verilog ../top.v
extract -map top.v -perm u x u
simple/scripts/extract_cant_open_map_file.ys 0 → 100644
read_verilog ../top.v
extract -map tt.v
simple/scripts/extract_cant_open_output.ys 0 → 100644
read_verilog ../top.v
extract -mine tt/out
simple/scripts/extract_counter_pout_without_args.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4
extract_counter -pout
design -reset
read_verilog ../top.v
write_verilog synth.v
simple/scripts/extract_map_and_mine.ys 0 → 100644
read_verilog ../top.v
extract -map top.v -mine out.ilang
simple/scripts/extract_mine_and_map.ys 0 → 100644
read_verilog ../top.v
extract -mine out.ilang -map top.v
simple/scripts/extract_missing_opt.ys 0 → 100644
read_verilog ../top.v
extract
simple/scripts/fsm_export_couldnt_open_file.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_export -o tt/fsm.kiss2
opt
fsm_opt
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_recode_cant_open_encfile.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_recode -encfile tt/file.fsm
opt
fsm_opt
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_recode_cant_open_fm_set_fsm_file.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_recode -fm_set_fsm_file tt/file.file
opt
fsm_opt
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/fsm_recode_encoding_isnt_supported.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_recode -encoding binari
opt
fsm_opt
tee -o result.log dump
synth -top top
write_verilog synth.v
simple/scripts/hierarchy_module_not_found.ys 0 → 100644
read_verilog ../top.v
hierarchy -top uu
synth -top top
write_verilog synth.v
simple/scripts/hierarchy_no_top_module.ys 0 → 100644
hierarchy -simcheck
synth -top top
write_verilog synth.v
simple/scripts/hierarchy_top_requires_args.ys 0 → 100644
read_verilog ../top.v
hierarchy -top
synth -top top
write_verilog synth.v
simple/scripts/memory_bram_cant_open_rules_file.ys 0 → 100644
read_verilog ../top.v
proc
memory_bram -rules uuu
tee -o result.log dump
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/memory_bram_syntax_error_in_rules.ys 0 → 100644
read_verilog ../top.v
proc
memory_bram -rules ../rules.v
tee -o result.log dump
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/nlutmap_error.ys 0 → 100644
read_verilog ../top.v
synth -top top
abc -lut 5
nlutmap -luts 6 -assert
tee -o result.log dump
write_verilog synth.v
simple/scripts/opt_lut_at_least_one_connection.ys 0 → 100644
read_verilog ../top.v
synth_ice40
ice40_unlut
opt_lut -dlogic a
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/opt_lut_invalid_format.ys 0 → 100644
read_verilog ../top.v
synth_ice40
ice40_unlut
opt_lut -dlogic a::a
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/prep_error.ys 0 → 100644
read_verilog ../top.v
select dffe
prep
synth -top top
write_verilog synth.v
simple/scripts/shregmap_match_clkpol.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -match -clkpol any
design -reset
read_verilog ../top.v
write_verilog synth.v
simple/scripts/shregmap_match_enpol.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -tech xilinx -match -enpol any
design -reset
read_verilog ../top.v
write_verilog synth.v
simple/scripts/shregmap_match_params.ys 0 → 100644
read_verilog ../top.v
shregmap -params -match 2:2
design -reset
read_verilog ../top.v
write_verilog synth.v
simple/scripts/shregmap_zinit_init.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -zinit -init
design -reset
read_verilog ../top.v
write_verilog synth.v
simple/scripts/submod_error.ys 0 → 100644
read_verilog ../top.v
proc
hierarchy
submod -name fsm -name fsm2
synth -top top
write_verilog synth.v
simple/scripts/zinit_failed_to_handle.ys 0 → 100644
read_verilog ../synth.v
zinit
tee -o result.log dump
write_verilog synth.v
simple/shregmap_error/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg in = 0;
wire [7:0] f;
top uut ( .clk(clk),
.in(in),
.out(f));
always @(posedge clk) begin
#3
in <= ~in;
end
assert_expr f_test(.clk(clk), .A(f[0]));
endmodule
module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A === 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
simple/shregmap_error/top.v 0 → 100644
module top (
out,
clk,
in
);
output [7:0] out;
input clk, in;
reg [7:0] out;
always @(posedge clk)
begin
`ifndef BUG
out <= out << 1;
out[0] <= in;
`else
out <= 8'bZZZZZZZZ;
`endif
end
endmodule
simple/submod_error/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
function [31:0] xorshift32;
input [31:0] arg;
begin
xorshift32 = arg;
// Xorshift32 RNG, doi:10.18637/jss.v008.i14
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
reg [31:0] rng = 123456789;
always @(posedge clk) rng <= xorshift32(rng);
wire a = xorshift32(rng * 5);
wire b = xorshift32(rng * 7);
reg rst;
wire g0;
wire g1;
top uut (
.a (a),
.b (b),
.clk (clk),
.rst (rst),
.g0(g0),
.g1(g1)
);
initial begin
rst <= 1;
#5
rst <= 0;
end
assert_Z g0_test(.clk(clk), .A(g0));
assert_Z g1_test(.clk(clk), .A(g1));
endmodule
simple/submod_error/top.v 0 → 100644
module fsm (
clock,
reset,
req,
gnt
);
input clock,reset;
inout [1:0] req ;
output [1:0] gnt ;
wire clock,reset;
wire [1:0] req ;
reg [1:0] gnt ;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101,GNT3 = 3'b111;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt[0] <= 0;
gnt[1] <= 0;
end else
case(state)
IDLE : if (req[0] == 1'b1) begin
state <= #1 GNT0;
`ifndef BUG
gnt[0] <= 1;
`else
gnt[0] <= 1'bZ;
`endif
end else if (req[1] == 1'b1) begin
gnt[1] <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (gnt[1] == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt[1] <= 0;
state <= #1 IDLE;
end
GNT1 : if (req[1] == 1'b1) begin
state <= #1 GNT2;
gnt[1] <= req[1];
end
GNT2 : if (gnt[0] == 1'b1) begin
state <= #1 GNT1;
gnt[1] <= req[1];
end
default : state <= #1 IDLE;
endcase
end
endmodule
module fsm2 (
clock,
reset,
req,
gnt
);
input clock,reset;
inout [1:0] req ;
output [1:0] gnt ;
wire clock,reset;
wire [1:0] req ;
reg [1:0] gnt ;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101,GNT3 = 3'b111;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt[0] <= 0;
gnt[1] <= 0;
end else
case(state)
IDLE : if (req[0] == 1'b1) begin
state <= #1 GNT0;
`ifndef BUG
gnt[0] <= 1;
`else
gnt[0] <= 1'bZ;
`endif
end else if (req[1] == 1'b1) begin
gnt[1] <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (gnt[1] == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt[1] <= 0;
state <= #1 IDLE;
end
GNT1 : if (req[1] == 1'b1) begin
state <= #1 GNT2;
gnt[1] <= req[1];
end
GNT2 : if (gnt[0] == 1'b1) begin
state <= #1 GNT1;
gnt[1] <= req[1];
end
default : state <= #1 IDLE;
endcase
end
endmodule
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
wire [1:0] g ;
wire [1:0] r ;
fsm u_fsm ( .clock(clk),
.reset(rst),
.req(r),
.gnt(g));
assign g0 = g[0];
assign g1 = g[1];
assign r[0] = a;
assign r[1] = b;
endmodule
simple/synth_error/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
simple/synth_error/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple/wreduce_div/testbench.v
......@@ -24,8 +24,10 @@ module testbench;
.cout(carryout)
);
assert_X out_test(.clk(in[0]), .A(out));
assert_X carry_test(.clk(in[0]), .A(carryout));
assign {patt_carry_out,patt_out} = in[2] % in[1] / in[0];
assert_Z out_test(in[0], out);
assert_Z carry_test(in[0], carryout);
endmodule
simple/wreduce_div/top.v
......@@ -11,7 +11,7 @@ module top
`ifndef BUG
assign {cout,A} = cin % y / x;
`else
assign {cout,A} = 2'bXX;
assign {cout,A} = 2'bZZ;
`endif
endmodule
simple/zinit_error/synth.v 0 → 100644
/* Generated by Yosys 0.8+492 (git sha1 2058c7c5, gcc 8.3.0-6ubuntu1~18.10 -Og -fPIC) */
(* cells_not_processed = 1 *)
(* src = "../top.v:1" *)
module adff(d, clk, clr, q);
(* src = "../top.v:6" *)
wire _0_;
(* src = "../top.v:3" *)
wire _1_;
(* src = "../top.v:2" *)
input clk;
(* src = "../top.v:2" *)
input clr;
(* src = "../top.v:2" *)
input d;
(* init = 1'h0 *)
(* src = "../top.v:2" *)
output q;
reg q = 1'h0;
always @(posedge clk or posedge clr)
if (clr)
q <= 1'h0;
else
q <= d;
assign _1_ = 1'h0;
assign _0_ = d;
endmodule
(* cells_not_processed = 1 *)
(* src = "../top.v:17" *)
module adffn(d, clk, clr, q);
(* src = "../top.v:22" *)
wire _0_;
(* src = "../top.v:19" *)
wire _1_;
(* src = "../top.v:23" *)
wire _2_;
(* src = "../top.v:18" *)
input clk;
(* src = "../top.v:18" *)
input clr;
(* src = "../top.v:18" *)
input d;
(* init = 1'h0 *)
(* src = "../top.v:18" *)
output q;
reg q = 1'h0;
assign _2_ = ! (* src = "../top.v:23" *) clr;
always @(posedge clk or negedge clr)
if (!clr)
q <= 1'h0;
else
q <= d;
assign _1_ = 1'h0;
assign _0_ = d;
endmodule
(* cells_not_processed = 1 *)
(* src = "../top.v:33" *)
module dffe(d, clk, en, q);
(* src = "../top.v:38" *)
wire _0_;
(* src = "../top.v:35" *)
wire _1_;
wire _2_;
wire _3_;
wire _4_;
(* src = "../top.v:34" *)
input clk;
(* src = "../top.v:34" *)
input d;
(* src = "../top.v:34" *)
input en;
(* init = 1'h0 *)
(* src = "../top.v:34" *)
output q;
reg q = 1'h0;
assign _2_ = en != 1'h0;
always @(posedge clk)
if (_2_)
q <= _3_;
assign _3_ = _4_ ? (* src = "../top.v:39" *) d : 1'hx;
assign _1_ = 1'h0;
assign _4_ = en;
assign _0_ = _3_;
endmodule
(* cells_not_processed = 1 *)
(* src = "../top.v:47" *)
module dffsr(d, clk, pre, clr, q);
(* src = "../top.v:52" *)
wire _00_;
(* src = "../top.v:49" *)
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
(* src = "../top.v:48" *)
input clk;
(* src = "../top.v:48" *)
input clr;
(* src = "../top.v:48" *)
input d;
(* src = "../top.v:48" *)
input pre;
(* init = 1'h0 *)
(* src = "../top.v:48" *)
output q;
assign _02_ = ~ 1'h1;
assign _03_ = ~ 1'h0;
assign _04_ = pre ? 1'h1 : 1'h0;
assign _05_ = clr ? 1'h0 : _04_;
assign _06_ = pre ? _02_ : 1'h0;
assign _07_ = clr ? _03_ : _06_;
reg [0:0] _14_ = 1'h0;
always @(posedge clk, posedge _05_, posedge _07_)
if (_07_) _14_[0] <= 1'b0;
else if (_05_) _14_[0] <= 1'b1;
else _14_[0] <= d;
assign q = _14_;
assign _01_ = 1'h0;
assign _00_ = d;
endmodule
(* cells_not_processed = 1 *)
(* src = "../top.v:65" *)
module ndffnsnr(d, clk, pre, clr, q);
(* src = "../top.v:70" *)
wire _00_;
(* src = "../top.v:67" *)
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
(* src = "../top.v:71" *)
wire _10_;
(* src = "../top.v:77" *)
wire _11_;
(* src = "../top.v:66" *)
input clk;
(* src = "../top.v:66" *)
input clr;
(* src = "../top.v:66" *)
input d;
(* src = "../top.v:66" *)
input pre;
(* init = 1'h0 *)
(* src = "../top.v:66" *)
output q;
assign _02_ = ~ 1'h1;
assign _03_ = ~ 1'h0;
assign _04_ = _08_ ? 1'h1 : 1'h0;
assign _05_ = _09_ ? 1'h0 : _04_;
assign _06_ = _08_ ? _02_ : 1'h0;
assign _07_ = _09_ ? _03_ : _06_;
assign _08_ = ~ pre;
assign _09_ = ~ clr;
assign _10_ = ! (* src = "../top.v:71" *) clr;
assign _11_ = ! (* src = "../top.v:77" *) pre;
reg [0:0] _22_ = 1'h0;
always @(negedge clk, posedge _05_, posedge _07_)
if (_07_) _22_[0] <= 1'b0;
else if (_05_) _22_[0] <= 1'b1;
else _22_[0] <= d;
assign q = _22_;
assign _01_ = 1'h0;
assign _00_ = d;
endmodule
(* cells_not_processed = 1 *)
(* src = "../top.v:83" *)
module top(clk, clr, pre, a, b, b1, b2, b3, b4);
(* src = "../top.v:87" *)
input a;
(* src = "../top.v:88" *)
output b;
(* src = "../top.v:88" *)
output b1;
(* src = "../top.v:88" *)
output b2;
(* src = "../top.v:88" *)
output b3;
(* src = "../top.v:88" *)
output b4;
(* src = "../top.v:84" *)
input clk;
(* src = "../top.v:85" *)
input clr;
(* src = "../top.v:86" *)
input pre;
(* module_not_derived = 32'd1 *)
(* src = "../top.v:107" *)
adff u_adff (
.clk(clk),
.clr(clr),
.d(a),
.q(b2)
);
(* module_not_derived = 32'd1 *)
(* src = "../top.v:114" *)
adffn u_adffn (
.clk(clk),
.clr(clr),
.d(a),
.q(b3)
);
(* module_not_derived = 32'd1 *)
(* src = "../top.v:121" *)
dffe u_dffe (
.clk(clk),
.d(a),
.en(clr),
.q(b4)
);
(* module_not_derived = 32'd1 *)
(* src = "../top.v:91" *)
dffsr u_dffsr (
.clk(clk),
.clr(clr),
.d(a),
.pre(pre),
.q(b)
);
(* module_not_derived = 32'd1 *)
(* src = "../top.v:99" *)
ndffnsnr u_ndffnsnr (
.clk(clk),
.clr(clr),
.d(a),
.pre(pre),
.q(b1)
);
endmodule
simple/zinit_error/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff = 0;
reg ndff= 1;
reg adff= 0;
reg adffn = 1'bX;
reg dffe = 1'bZ;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
simple/zinit_error/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 1'bX;
q = 3'b111;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 1'bZ;
end
always @( posedge clk, posedge en )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 1;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
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