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yosys-tests
Unverified Commit 14623819 by Miodrag Milanović Committed by GitHub
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Merge pull request #37 from SergeyDegtyar/master 

Add tests for error messages in 'misc' test group.
parents 2934eb5b 971f4827
Showing with 2630 additions and 8 deletions
architecture/scripts/synth_xilinx_nosrt.ys 0 → 100644
read_verilog ../top.v
synth_xilinx -nosrl
write_verilog synth.v
misc/Makefile
......@@ -24,6 +24,7 @@ $(eval $(call template,test_abcloop,test_abcloop test_abcloop_n test_abcloop_s )
#test_cell_map - takes a lot of time
# test_cell_mux, test_cell_pmux - is not supported
$(eval $(call template,test_cell,test_cell test_cell_aigmap test_cell_const test_cell_edges test_cell_f test_cell_div test_cell_muxdiv test_cell_n test_cell_noeval test_cell_nosat test_cell_s test_cell_script test_cell_simlib test_cell_v test_cell_vlog test_cell_w test_cell_alu test_cell_sop test_cell_lut test_cell_macc test_cell_lcu test_cell_fa))
$(eval $(call template,test_cell_error, test_cell_failed_to_open test_cell_unexpected_opt test_cell_cell_type_not_supported test_cell_no_cell_t_specified test_cell_dont_spec_cell_type_with_f ))
#torder
$(eval $(call template,torder,torder torder_stop torder_noautostop ))
......@@ -34,18 +35,21 @@ $(eval $(call template,trace_mem,trace_mem ))
#write_file
$(eval $(call template,write_file,write_file write_file_a ))
$(eval $(call template,write_file_error,write_file_missing_name write_file_a_missing_name ))
#stat
$(eval $(call template,stat, stat stat_top stat_width stat_liberty stat_tech_xilinx))
$(eval $(call template,stat, stat stat_top stat_width stat_liberty stat_tech_xilinx ))
$(eval $(call template,stat_error, stat_unsupported_tech stat_cant_find_module stat_cant_open_lib_file ))
#show
# show_pause - skipped
$(eval $(call template,show, show show_colorattr show_colors show_color show_enum show_format show_label show_lib show_long show_notitle show_prefix show_signed show_stretch show_viewer show_width))
$(eval $(call template,show_error, show_only_one_module show_cant_open_dot_file show_cant_open_lib_file show_nothing_there_to_show))
#scc
$(eval $(call template,scc, scc scc_all_cell_types scc_expect scc_max_depth scc_nofeedback scc_select scc_set_attr ))
$(eval $(call template,scc_feedback, scc scc_all_cell_types scc_expect1 scc_max_depth scc_nofeedback scc_select scc_set_attr ))
$(eval $(call template,scc_hier_feedback, scc scc_all_cell_types scc_expect scc_max_depth scc_nofeedback scc_select scc_set_attr ))
$(eval $(call template,scc_error, scc_expect1 ))
#scatter
......@@ -53,6 +57,7 @@ $(eval $(call template,scatter, scatter ))
#rename
$(eval $(call template,rename, rename rename_top rename_src rename_hide rename_enumerate rename_enumerate_pat rename_wire rename_top_top rename_low))
$(eval $(call template,rename_error, rename_obj_not_found rename_no_top_module rename_invalid_number_of_args rename_invalid_number_of_args_top rename_mode_out_requires))
#qwp
#qwp_v - exception (issue #923)
......@@ -72,12 +77,14 @@ $(eval $(call template,delete_mem, delete_mem ))
#cover
$(eval $(call template,cover, cover cover_q cover_o cover_dir cover_a ))
$(eval $(call template,cover_error, cover_cant_create_file ))
#insbuf
$(eval $(call template,insbuf,insbuf insbuf_cell))
#add
$(eval $(call template,add, add add_wire add_input add_output add_inout add_global_input ))
$(eval $(call template,add_error, add_error ))
#blackbox
$(eval $(call template,blackbox, blackbox ))
......@@ -85,22 +92,27 @@ $(eval $(call template,blackbox, blackbox ))
# - issue #925
#bugpoint ERROR: No such command: autoidx (type 'help' for a command overview)
$(eval $(call template,bugpoint,bugpoint_yosys bugpoint_script bugpoint_grep bugpoint_fast bugpoint_clean bugpoint_modules bugpoint_ports bugpoint_cells bugpoint_connections ))
$(eval $(call template,bugpoint_error, bugpoint_missing_script bugpoint_do_not_crash bugpoint_fully_selected_des))
#bugpoint_grep_string_not_found - no error
#chformal
$(eval $(call template,chformal, chformal chformal_assert2assume chformal_assert chformal_assume2assert chformal_assume chformal_cover chformal_delay chformal_early chformal_proc_early chformal_fair2live_assert2assume chformal_fair2live chformal_fair chformal_live2fair chformal_live chformal_skip ))
$(eval $(call template,chformal_dff, chformal chformal_assert2assume chformal_assert chformal_assume2assert chformal_assume chformal_cover chformal_delay chformal_early chformal_proc_early chformal_fair2live_assert2assume chformal_fair2live chformal_fair chformal_live2fair chformal_live chformal_skip ))
$(eval $(call template,chformal_error, chformal_error ))
#chtype
$(eval $(call template,chtype, chtype chtype_map chtype_selection chtype_set))
#connect
$(eval $(call template,connect, connect_nomap_set connect_nomap_unset connect_nounset_set connect_set connect_unset connect_port connect_nomap_port))
$(eval $(call template,connect_error, connect_multiple_modules connect_found_process connect_no_modules connect_set_with_unset connect_set_with_port connect_set_with_unset_and_port connect_cannot_parse_set_lhs_expr connect_cannot_parse_set_rhs_expr connect_unset_with_nounset connect_unset_with_port connect_unset_with_nounset_and_port connect_failed_parse_unset connect_port_with_nounset connect_cant_find_cell connect_failed_to_parse_port_expr connect_opt_expected))
#connwrappers
$(eval $(call template,connwrappers, connwrappers connwrappers_signed connwrappers_unsigned connwrappers_port ))
#plugin
$(eval $(call template,plugin, plugin plugin_i plugin_a plugin_l ))
$(eval $(call template,plugin_error, plugin_error ))
#select
$(eval $(call template,select, select select_all select_add select_add_all select_assert_any select_assert_count select_assert_max select_assert_min select_assert_none select_clear select_count select_del select_list select_module select_none select_read select_set select_write select_add_A_eq select_add_a_eq select_add_A_lesseq select_add_a_lesseq select_add_A_less select_add_a_less select_add_A_moreeq select_add_a_moreeq select_add_A_more select_add_a_more select_add_A select_add_a select_add_c select_add_i select_add_mid select_add_m select_add_n select_add_obj select_add_o select_add_p select_add_r_eq select_add_r_lesseq select_add_r_less select_add_r_moreeq select_add_r_more select_add_r select_add_ss select_add_s select_add_t select_add_w select_add_x ))
......@@ -108,39 +120,52 @@ $(eval $(call template,select_mem, select select_all select_add select_add_all s
$(eval $(call template,select_ls, select_ls select_ls_top))
$(eval $(call template,select_cd, select_cd select_cd_up select_cd_module ))
$(eval $(call template,select_stack,select_%a select_%cie select_%ci select_%coe select_%co select_%C select_%c select_%i select_%M select_%m select_%n select_%R4 select_%R select_%s select_%u select_%x_%D select_%x_%d select_%xe select_%))
$(eval $(call template,select_error, select_add_with_del select_assert_any_failed select_assert_any_with_count select_assert_count_failed select_assert_list_with_assert_max select_assert_list_with_del select_assert_max_failed select_assert_max_with_del select_assert_min_failed select_assert_none_failed select_assert_none_with_min select_cant_open_for_reading select_cant_open_for_writing select_clear_with_other_opt select_count_with_assert_min select_count_with_assert_none select_error_in_expand_op select_none_with_other_opt select_no_sel_to_check_as_any select_no_sel_to_check_as_count select_no_sel_to_check_as_max select_no_sel_to_check_as_min select_no_sel_to_check_as_none select_no_such_module select_nothing_to_add select_nothing_to_del select_one_elem_for__a select_one_elem_for__cie select_one_elem_for__ci select_one_elem_for__coe select_one_elem_for__co select_one_elem_for__C select_one_elem_for__c select_one_elem_for__D select_one_elem_for__d select_one_elem_for__i select_one_elem_for__m select_one_elem_for__M select_one_elem_for__n select_one_elem_for__R select_one_elem_for__s select_one_elem_for__u select_one_elem_for__xe select_one_elem_for__x select_read_with_selection_expr select_selection_isnt_defined select_set_with_assert_any select_set_with_assert_max select_set_with_count select_set_with_del select_set_with_list select_unknown_opt select_unknown_selection select_write_with_assert_count select_write_with_del))
$(eval $(call template,select_cd_error, select_cd_invalid_number_of_args select_cd_no_such_module ))
#setattr
$(eval $(call template,setattr, setattr setattr_mod setattr_set setattr_top setattr_unset setattr_set_proc ))
$(eval $(call template,setattr_mem, setattr setattr_mod setattr_set setattr_top setattr_unset setattr_set_proc ))
$(eval $(call template,setattr_error, setattr_cant_decode_value ))
#setparam
#setparam_type - issue #926
#ERROR: Found error in internal cell \top.$procdff$4 ($dff) at kernel/rtlil.cc:715:
$(eval $(call template,setparam, setparam setparam_set setparam_unset setparam_top setparam_type))
#chparam
$(eval $(call template,chparam, chparam chparam_set chparam_top chparam_list ))
$(eval $(call template,chparam_error, chparam_error))
#setundef
$(eval $(call template,setundef, setundef_one setundef_anyseq setundef_anyconst setundef_init setundef_random setundef_undef setundef_undriven setundef_expose))
# issue #1092
$(eval $(call template,setundef_error, setundef_expose_without_undriven setundef_init_with_anyconst setundef_init_with_anyseq setundef_one_of_options setundef_undriven_with_process))
#assertpmux
$(eval $(call template,assertpmux, assertpmux assertpmux_noinit assertpmux_always))
#eval
$(eval $(call template,eval, eval eval_set eval_set_undef eval_table eval_show eval_brute_force_equiv_checker eval_show_not_set eval_table_set eval_vloghammer_report eval_vloghammer_report_rtl))
$(eval $(call template,eval_error, eval_only_one_module eval_failed_to_parse_lhs eval_failed_to_parse_rhs eval_rhs_expr eval_diff_lhs_rhs_sizes eval_failed_to_parse_show_expr eval_failed_to_parse_table_expr eval_empty_selection eval_port_doesnt_match eval_cant_find_mod_1 eval_cant_find_mod_2 eval_mods_arent_equiv eval_cant_find_mod_in_curr_des eval_no_output_wire eval_cant_find_input eval_wire_isnt_an_input eval_failed_to_parse_pattern eval_pattern_is_to_short eval_two_distinct_solutions))
#freduce
$(eval $(call template,freduce, freduce freduce_v freduce_vv freduce_inv freduce_stop freduce_dump ))
$(eval $(call template,freduce_dff, freduce freduce_v freduce_vv freduce_inv freduce_stop freduce_dump ))
$(eval $(call template,freduce_mem, freduce freduce_v freduce_vv freduce_inv freduce_stop freduce_dump ))
$(eval $(call template,freduce_error, freduce_logic_loop ))
#miter -assert
$(eval $(call template,miter_assert, miter_assert miter_assert_flatten ))
$(eval $(call template,miter_assert_assume, miter_assert miter_assert_flatten ))
$(eval $(call template,miter_error, miter_cant_find_gate_module miter_cant_find_gold_module miter_cant_find_module miter_missing_mode_param miter_no_match_in_gate miter_no_match_in_gold miter_there_is_already_a_module ))
#sat
#sat_tempinduct_def sat_tempinduct_tempinduct_def - issue #883
#ERROR: Assert `!undef_mode || model_undef' failed in ./kernel/satgen.h:90.
$(eval $(call template,sat, sat_dump_cnf sat_dump_json sat_dump_vcd sat_initsteps sat_maxsteps sat_max sat_prove_x sat_set_all_undef_at sat_set_all_undef sat_set_any_undef_at sat_set_any_undef sat_set_def_at sat_set_def sat_set_init sat_set sat_show sat_stepsize sat_tempinduct_skip sat_unset_at sat_set_at sat_seq sat_prove_skip sat_timeout sat_prove sat_tempinduct sat sat_all sat_ignore_unknown_cells sat_enable_undef sat_max_undef sat_show_inputs sat_show_outputs sat_show_ports sat_show_regs sat_show_public sat_show_all sat_set_assumes sat_set_init_undef sat_set_init_def sat_set_init_zero sat_tempinduct_baseonly sat_tempinduct_inductonly sat_verify sat_verify_no_timeout sat_falsify sat_falsify_no_timeout sat_prove_asserts sat_tempinduct_tempinduct_baseonly sat_set_def_inputs sat_tempinduct_baseonly_maxsteps ))
$(eval $(call template,sat, sat_dump_cnf sat_dump_json sat_dump_vcd sat_initsteps sat_maxsteps sat_max sat_prove_x sat_set_all_undef_at sat_set_all_undef sat_set_any_undef_at sat_set_any_undef sat_set_def_at sat_set_def sat_set_init sat_set sat_show sat_stepsize sat_tempinduct_skip sat_unset_at sat_set_at sat_seq sat_prove_skip sat_timeout sat_prove sat_tempinduct sat sat_all sat_ignore_unknown_cells sat_enable_undef sat_max_undef sat_show_inputs sat_show_outputs sat_show_ports sat_show_regs sat_show_public sat_show_all sat_set_assumes sat_set_init_undef sat_set_init_def sat_set_init_zero sat_tempinduct_baseonly sat_tempinduct_inductonly sat_verify sat_verify_no_timeout sat_falsify sat_falsify_no_timeout sat_prove_asserts sat_tempinduct_tempinduct_baseonly sat_set_def_inputs sat_tempinduct_baseonly_maxsteps sat_tempinduct_def sat_tempinduct_tempinduct_def))
$(eval $(call template,sat_error, sat_show_fail sat_provex_diff_size sat_provex_lhs_fail sat_provex_rhs_fail sat_prove_rhs_fail sat_prove_lhs_fail sat_prove_diff_size sat_set_all_undef_fail sat_set_any_undef_fail sat_set_def_fail sat_set_diff_size sat_set_rhs_fail sat_set_lhs_fail sat_cnf_open_json_file sat_cant_open_json_file sat_cant_open_vcd_file sat_falsify_fail sat_verify_fail sat_all_with_tempinduct sat_maxundef_with_tempinduct sat_max_with_tempinduct sat_max_max_undef_with_tempinduct sat_max_all_with_tempinduct sat_max_maxundef_with_tempinduct sat_max_maxundef_all_with_tempinduct sat_maxsteps_only_for_tempinduct sat_si_def_zero sat_si_undef_zero sat_si_def_undef sat_si_def_undef_zero sat_failed_to_import_cell sat_prove_skip_must_be_smaller_than_seq sat_prove_and_tempinduct sat_got_tempinduct_but_nothing_to_prove sat_cant_perform_sat_on_empty_sel sat_only_one_module_must_be_sel))
#sat_set_all_undef_at_fail sat_set_any_undef_at_fail sat_set_def_at_fail sat_unset_at_fail sat_set_at_diff_size sat_set_at_lhs_fail sat_set_at_rhs_fail - no errors
#sim
$(eval $(call template,sim,sim sim_a sim_clock sim_d sim_n sim_rstlen sim_vcd sim_w sim_zinit ))
......@@ -152,6 +177,7 @@ $(eval $(call template,splitnets_logic, splitnets splitnets_format splitnets_por
#splice
$(eval $(call template,splice, splice splice_sel_by_cell splice_sel_by_wire splice_sel_any_bit splice_wires splice_no_outputs splice_port splice_no_port ))
$(eval $(call template,splice_error, splice_sel_by_cell_and_sel_by_wire splice_sel_by_cell_and_sel_any_bit splice_port_and_no_port ))
#supercover
$(eval $(call template,supercover, supercover))
......@@ -161,15 +187,18 @@ $(eval $(call template,rmports, rmports))
#check
$(eval $(call template,check, check check_noinit check_initdrv check_assert))
$(eval $(call template,check_error, check_error ))
#design
$(eval $(call template,design, design_import design_copy_from design_copy_to design_as))
$(eval $(call template,design_error, design_no_saved_design_copy_from design_no_saved_design_import design_no_saved_design_load design_no_pushed_design design_no_top_module))
#log
$(eval $(call template,log, log log_stdout log_stderr log_nolog log_n))
#tee
$(eval $(call template,tee, tee))
$(eval $(call template,tee_error, tee_o_cant_create_file tee_a_cant_create_file ))
#test_autotb
$(eval $(call template,test_autotb, test_autotb test_autotb_file test_autotb_n test_autotb_seed))
......@@ -177,8 +206,8 @@ $(eval $(call template,test_autotb, test_autotb test_autotb_file test_autotb_n t
#abc
$(eval $(call template,abc, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S abc_dff))
$(eval $(call template,abc_dff, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S abc_dff))
$(eval $(call template,abc_mux, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S))
$(eval $(call template,abc_error, abc_cannot_open abc_constr_no_liberty abc_lut_liberty abc_unsup_gate_type abc_inv_luts_synt abc_dff abc_return_code abc_clk_domain_not_found abc_script_o abc_script_top))
$(eval $(call template,abc_mux, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S abc_dff))
$(eval $(call template,abc_error, abc_cannot_open abc_constr_no_liberty abc_lut_liberty abc_unsup_gate_type abc_inv_luts_synt abc_return_code abc_clk_domain_not_found abc_script_o abc_script_top))
#hilomap
$(eval $(call template,hilomap, hilomap hilomap_hicell hilomap_locell hilomap_singleton hilomap_hicell_singleton hilomap_locell_singleton hilomap_hicell_locell_singleton))
......@@ -189,9 +218,12 @@ $(eval $(call template,cutpoint, cutpoint cutpoint_undef))
#mutate
$(eval $(call template,mutate, mutate_list mutate_cnot1 mutate_cnot0 mutate_const1 mutate_const0 mutate_inv mutate_all mutate_list_cfg mutate_list_ctrl mutate_list_none mutate_list_o mutate_list_seed mutate_list_s))
$(eval $(call template,mutate_mem, mutate_list mutate_all))
$(eval $(call template,mutate_error, mutate_error))
#fmconbine
#fmcombine_gate_cell_not_found - failed #1063
$(eval $(call template,fmcombine, fmcombine fmcombine_fwd fmcombine_bwd fmcombine_nop fmcombine_bwd_fwd fmcombine_anyeq fmcombine_initeq))
$(eval $(call template,fmcombine_error, fmcombine_invalid_number_of_param fmcombine_module_not_found fmcombine_gold_cell_not_found fmcombine_gate_cell_not_found fmcombine_types_not_match fmcombine_nop_with_fwd fmcombine_nop_with_bwd fmcombine_nop_with_fwd_bwd))
#pmuxtree
$(eval $(call template,pmuxtree, pmuxtree))
......
misc/add_error/top.v 0 → 100644
(* black_box *) module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
misc/bugpoint_error/script.ys 0 → 100644
read_verilog ../top2.v
abc -g cmos4
misc/bugpoint_error/top.v 0 → 100644
module bb
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module top
(
input x,
input y,
input cin,
output A,
output cout
);
bb u_bb (x,y,cin,A,cout);
endmodule
misc/bugpoint_error/top2.v 0 → 100644
module bb2
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module top2
(
input x,
input y,
input cin,
output A,
output cout
);
bb2 u_bb2 (x,y,cin,A,cout);
endmodule
misc/check/top.v
module top
( input d, clk, output reg q );
wire u;
always @( posedge clk )
q <= d;
endmodule
misc/check/top1.v 0 → 100644
module top
( input d, clk, output reg q );
wire u;
wire s;
assign u = s;
assign u = d;
assign u = clk;
always @( posedge clk )
q <= u;
endmodule
misc/check_error/top.v 0 → 100644
module top
( input d, clk, output reg q );
wire u;
wire s;
assign u = s;
assign u = d;
assign u = clk;
always @( posedge clk )
q <= u;
endmodule
misc/chformal_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg ASSERT = 1;
(* anyconst *) reg foo;
(* anyseq *) reg too;
initial begin
begin
A = 0;
cout = 0;
end
end
`ifndef BUG
always @(posedge x) begin
if ($initstate)
A <= 0;
A <= y + cin + too;
assume(too);
assume(s_eventually too);
end
always @(negedge x) begin
if ($initstate)
cout <= 0;
cout <= y + A + foo;
assert(ASSERT);
assert(s_eventually ASSERT);
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
misc/chparam_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
wire o;
parameter X = 1;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (x,y,o);
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/connect_error/top.v 0 → 100644
module top
( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
misc/connect_error/top_2.v 0 → 100644
module top
( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
module top2
( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
misc/cover_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
misc/design_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
//assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/eval_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (.x(x),.o(o),.y(1'b0));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
wire w;
assign o = x + y;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/eval_error/top_err_1.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
wire w;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (.x(x),.o(o),.y(1'b0));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
// input y,
output o
);
assign o = x;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/eval_error/top_err_2.v 0 → 100644
module top
(
input [7:0] x,
input[7:0] y,
input cin,
output reg [7:0] A,
output [7:0] cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle #(7) u_mid (.x(x),.o(o),.y(1'b0));
middle #(0) u_mid2 (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
x,
y,
o
);
parameter u = 7;
input [u:0] x;
input [u:0] y;
output [u:0] o;
assign o = x + y;
endmodule
module xiddle
(
input [1:0] x,
input y,
output [1:0] o
);
assign o = x + y;
endmodule
misc/eval_error/top_err_3.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (.x(x),.o(o),.y(1'b0));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
wire w;
assign o = x + y;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/fmcombine_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid1 (.x(x),.o(o),.y(1'b0));
middle u_mid2 (.x(x),.o(o),.y(1'b1));
middle u_mid3 (.x(x),.o(o),.y(1'bX));
middle u_mid4 (.x(x),.o(o),.y(1'bX));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
urtl u_urtl (.x(x),.o(o),.y(y));
endmodule
module urtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/fmcombine_error/top_err_1.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
parameter U = "string";
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid1 (.x(x),.o(o),.y(1'b0));
middle u_mid2 (.x(x),.o(o),.y(1'b1));
middle u_mid3 (.x(x),.o(o),.y(1'bX));
middle u_mid4 (.x(x),.o(o),.y(1'bX));
urtl u_urtl (.x(x),.o(o),.y(y));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
parameter u = 12;
urtl u_urtl (.x(x),.o(o),.y(y));
endmodule
module urtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/freduce_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
//assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/freduce_error/top_err_1.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
//assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
u_rtl inst_u_rtl (.x(o),.o(x));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
wire ll;
assign ll = x & o;
assign o = y & ll;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/miter_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
//assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/miter_error/top_err_1.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
//assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module u_rtl
(
input x,
// input y,
output o
);
assign o = x;
endmodule
misc/mutate_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
misc/plugin_error/top.v 0 → 100644
module top
( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
misc/rename_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (x,y,o);
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
wire dd;
assign o = x + y;
endmodule
module low ();
endmodule
misc/run.sh
......@@ -14,7 +14,7 @@ cd $1/work_$2
touch .start
# cases where 'syntax error' or other errors are expected
if [ "$1" = "abc_error" ]; then
if echo "$1" | grep ".*_error"; then
expected_string=""
#Change checked string for check other errors
......@@ -28,6 +28,8 @@ if [ "$1" = "abc_error" ]; then
expected_string="ERROR: Command syntax error: Unsupported gate type:"
elif [ "$2" = "abc_inv_luts_synt" ]; then
expected_string="Invalid -luts syntax"
elif [ "$2" = "abc_dff" ]; then
expected_string="Unknown option or option in arguments"
elif [ "$2" = "abc_return_code" ]; then
expected_string="failed: return code"
elif [ "$2" = "abc_clk_domain_not_found" ]; then
......@@ -36,8 +38,346 @@ if [ "$1" = "abc_error" ]; then
expected_string="ERROR: Can't open ABC output file"
elif [ "$2" = "abc_script_top" ]; then
expected_string="ERROR: Can't open ABC output file"
elif [ "$2" = "add_error" ]; then
expected_string="ERROR: Found incompatible object with same name in module"
elif [ "$2" = "bugpoint_missing_script" ]; then
expected_string="ERROR: Missing -script option"
elif [ "$2" = "bugpoint_do_not_crash" ]; then
expected_string="ERROR: The provided script file and Yosys binary do not crash on this design"
elif [ "$2" = "bugpoint_grep_string_not_found" ]; then
expected_string="ERROR: The provided grep string is not found in the log file"
elif [ "$2" = "bugpoint_fully_selected_des" ]; then
expected_string="ERROR: This command only operates on fully selected designs"
elif [ "$2" = "check_error" ]; then
expected_string="ERROR: Found 1 problems in 'check -assert'"
elif [ "$2" = "chformal_error" ]; then
expected_string="ERROR: Mode option is missing"
elif [ "$2" = "chparam_error" ]; then
expected_string="ERROR: The options -set and -list cannot be used together"
elif [ "$2" = "connect_multiple_modules" ]; then
expected_string="ERROR: Multiple modules selected:"
elif [ "$2" = "connect_found_process" ]; then
expected_string="ERROR: Found processes in selected module"
elif [ "$2" = "connect_no_modules" ]; then
expected_string="ERROR: No modules selected."
elif [ "$2" = "connect_set_with_unset" ] || \
[ "$2" = "connect_set_with_port" ] || \
[ "$2" = "connect_set_with_unset_and_port" ]; then
expected_string="ERROR: Can't use -set together with -unset and/or -port."
elif [ "$2" = "connect_cannot_parse_set_lhs_expr" ]; then
expected_string="ERROR: Failed to parse set lhs expression"
elif [ "$2" = "connect_cannot_parse_set_rhs_expr" ]; then
expected_string="ERROR: Failed to parse set rhs expression"
elif [ "$2" = "connect_unset_with_nounset" ] || \
[ "$2" = "connect_unset_with_port" ] || \
[ "$2" = "connect_unset_with_nounset_and_port" ]; then
expected_string="ERROR: Can't use -unset together with -port and/or -nounset."
elif [ "$2" = "connect_failed_parse_unset" ]; then
expected_string="ERROR: Failed to parse unset expression"
elif [ "$2" = "connect_port_with_nounset" ]; then
expected_string="ERROR: Can't use -port together with -nounset."
elif [ "$2" = "connect_cant_find_cell" ]; then
expected_string="ERROR: Can't find cell"
elif [ "$2" = "connect_failed_to_parse_port_expr" ]; then
expected_string="ERROR: Failed to parse port expression"
elif [ "$2" = "connect_opt_expected" ]; then
expected_string="Expected -set, -unset, or -port."
elif [ "$2" = "cover_cant_create_file" ]; then
expected_string="ERROR: Can't create file"
elif [ "$2" = "design_no_saved_design_copy_from" ] || \
[ "$2" = "design_no_saved_design_import" ] || \
[ "$2" = "design_no_saved_design_load" ]; then
expected_string="ERROR: No saved design"
elif [ "$2" = "design_no_pushed_design" ]; then
expected_string="ERROR: No pushed designs"
elif [ "$2" = "design_no_top_module" ]; then
expected_string="ERROR: No top module found in source design."
elif [ "$2" = "eval_only_one_module" ]; then
expected_string="ERROR: Only one module must be selected for the EVAL pass!"
elif [ "$2" = "eval_failed_to_parse_lhs" ]; then
expected_string="ERROR: Failed to parse lhs set expression"
elif [ "$2" = "eval_failed_to_parse_rhs" ]; then
expected_string="ERROR: Failed to parse rhs set expression"
elif [ "$2" = "eval_rhs_expr" ]; then
expected_string="ERROR: Right-hand-side set expression"
elif [ "$2" = "eval_diff_lhs_rhs_sizes" ]; then
expected_string="ERROR: Set expression with different lhs and rhs sizes:"
elif [ "$2" = "eval_failed_to_parse_show_expr" ]; then
expected_string="ERROR: Failed to parse show expression"
elif [ "$2" = "eval_failed_to_parse_table_expr" ]; then
expected_string="ERROR: Failed to parse table expression"
elif [ "$2" = "eval_empty_selection" ]; then
expected_string="ERROR: Can't perform EVAL on an empty selection!"
elif [ "$2" = "eval_port_doesnt_match" ]; then
expected_string="in module 1 does not match its counterpart in module 2!"
elif [ "$2" = "eval_has_no_counterpart" ]; then
expected_string="in module 1 has no counterpart in module 2!"
elif [ "$2" = "eval_cant_find_mod_1" ] || \
[ "$2" = "eval_cant_find_mod_2" ]; then
expected_string="ERROR: Can't find module"
elif [ "$2" = "eval_mods_arent_equiv" ]; then
expected_string="ERROR: Modules are not equivalent!"
elif [ "$2" = "eval_cant_find_mod_in_curr_des" ]; then
expected_string="ERROR: Can't find module dle in current design!"
elif [ "$2" = "eval_no_output_wire" ]; then
expected_string="ERROR: No output wire"
elif [ "$2" = "eval_cant_find_input" ]; then
expected_string="ERROR: Can't find input s in module middle!"
elif [ "$2" = "eval_wire_isnt_an_input" ]; then
expected_string="ERROR: Wire w in module middle is not an input!"
elif [ "$2" = "eval_failed_to_parse_pattern" ]; then
expected_string="ERROR: Failed to parse pattern d!"
elif [ "$2" = "eval_pattern_is_to_short" ]; then
expected_string="ERROR: Pattern 1'b1 is to short!"
elif [ "$2" = "eval_two_distinct_solutions" ]; then
expected_string="ERROR: Found two distinct solutions to SAT problem."
elif [ "$2" = "fmcombine_invalid_number_of_param" ]; then
expected_string="ERROR: Invalid number of arguments."
elif [ "$2" = "fmcombine_module_not_found" ]; then
expected_string="ERROR: Module topp not found."
elif [ "$2" = "fmcombine_gold_cell_not_found" ]; then
expected_string="ERROR: Gold cell u_mid8 not found in module top."
elif [ "$2" = "fmcombine_gate_cell_not_found" ]; then
expected_string="ERROR: Gate cell u_mid8 not found in module top."
elif [ "$2" = "fmcombine_types_not_match" ]; then
expected_string="ERROR: Types of gold and gate cells do not match."
elif [ "$2" = "fmcombine_nop_with_fwd" ] || \
[ "$2" = "fmcombine_nop_with_bwd" ] || \
[ "$2" = "fmcombine_nop_with_fwd_bwd" ]; then
expected_string="ERROR: Option -nop can not be combined with -fwd and/or -bwd."
elif [ "$2" = "freduce_logic_loop" ]; then
expected_string="ERROR: Found logic loop:"
elif [ "$2" = "miter_cant_find_gate_module" ]; then
expected_string="ERROR: Can't find gate module"
elif [ "$2" = "miter_cant_find_gold_module" ]; then
expected_string="ERROR: Can't find gold module"
elif [ "$2" = "miter_cant_find_module" ]; then
expected_string="ERROR: Can't find module"
elif [ "$2" = "miter_missing_mode_param" ]; then
expected_string="ERROR: Missing mode parameter!"
elif [ "$2" = "miter_no_match_in_gate" ]; then
expected_string="ERROR: No matching port in gate module was found for"
elif [ "$2" = "miter_no_match_in_gold" ]; then
expected_string="ERROR: No matching port in gold module was found for"
elif [ "$2" = "miter_there_is_already_a_module" ]; then
expected_string="ERROR: There is already a module"
elif [ "$2" = "mutate_error" ]; then
expected_string="ERROR: Invalid mode:"
elif [ "$2" = "plugin_error" ]; then
expected_string="ERROR: Can't load module"
elif [ "$2" = "rename_obj_not_found" ]; then
expected_string="ERROR: Object \`u' not found!"
elif [ "$2" = "rename_no_top_module" ]; then
expected_string="ERROR: No top module found!"
elif [ "$2" = "rename_invalid_number_of_args" ] || \
[ "$2" = "rename_invalid_number_of_args_top" ]; then
expected_string="ERROR: Invalid number of arguments!"
elif [ "$2" = "rename_mode_out_requires" ]; then
expected_string="ERROR: Mode -output requires that there is an active module selected."
elif [ "$2" = "sat_show_fail" ]; then
expected_string="ERROR: Failed to parse show expression"
elif [ "$2" = "sat_provex_diff_size" ]; then
expected_string="ERROR: Proof-x expression with different lhs and rhs sizes:"
elif [ "$2" = "sat_provex_lhs_fail" ]; then
expected_string="ERROR: Failed to parse lhs proof-x expression "
elif [ "$2" = "sat_provex_rhs_fail" ]; then
expected_string="ERROR: Failed to parse rhs proof-x expression "
elif [ "$2" = "sat_prove_rhs_fail" ]; then
expected_string="ERROR: Failed to parse rhs proof expression "
elif [ "$2" = "sat_prove_lhs_fail" ]; then
expected_string="ERROR: Failed to parse lhs proof expression "
elif [ "$2" = "sat_prove_diff_size" ]; then
expected_string="ERROR: Proof expression with different lhs and rhs sizes:"
elif [ "$2" = "sat_set_all_undef_at_fail" ] || \
[ "$2" = "sat_set_any_undef_at_fail" ] || \
[ "$2" = "sat_set_def_at_fail" ] || \
[ "$2" = "sat_set_all_undef_fail" ] || \
[ "$2" = "sat_set_any_undef_fail" ] || \
[ "$2" = "sat_set_def_fail" ]; then
expected_string="ERROR: Failed to parse set-def expression "
elif [ "$2" = "sat_unset_at_fail" ]; then
expected_string="ERROR: Failed to parse lhs set expression "
elif [ "$2" = "sat_set_at_diff_size" ]; then
expected_string="ERROR: Set expression with different lhs and rhs sizes:"
elif [ "$2" = "sat_set_at_lhs_fail" ]; then
expected_string="ERROR: Failed to parse lhs set expression"
elif [ "$2" = "sat_set_at_rhs_fail" ]; then
expected_string="ERROR: Failed to parse rhs set expression"
elif [ "$2" = "sat_set_diff_size" ]; then
expected_string="ERROR: Set expression with different lhs and rhs sizes:"
elif [ "$2" = "sat_set_rhs_fail" ]; then
expected_string="ERROR: Failed to parse rhs set expression"
elif [ "$2" = "sat_set_lhs_fail" ]; then
expected_string="ERROR: Failed to parse lhs set expression"
elif [ "$2" = "sat_cnf_open_json_file" ] || \
[ "$2" = "sat_cant_open_json_file" ] || \
[ "$2" = "sat_cant_open_vcd_file" ] ; then
expected_string="ERROR: Can't open output file"
elif [ "$2" = "sat_falsify_fail" ]; then
expected_string="ERROR: Called with -falsify and found a model"
elif [ "$2" = "sat_verify_fail" ]; then
expected_string="ERROR: Called with -verify and proof did fail!"
elif [ "$2" = "sat_all_with_tempinduct" ] || \
[ "$2" = "sat_maxundef_with_tempinduct" ] || \
[ "$2" = "sat_max_with_tempinduct" ] || \
[ "$2" = "sat_max_max_undef_with_tempinduct" ] || \
[ "$2" = "sat_max_all_with_tempinduct" ] || \
[ "$2" = "sat_max_maxundef_with_tempinduct" ] || \
[ "$2" = "sat_max_maxundef_all_with_tempinduct" ]; then
expected_string="ERROR: The options -max, -all, and -max_undef are not supported for temporal induction proofs!"
elif [ "$2" = "sat_maxsteps_only_for_tempinduct" ]; then
expected_string="ERROR: The options -maxsteps is only supported for temporal induction proofs!"
elif [ "$2" = "sat_si_def_zero" ] || \
[ "$2" = "sat_si_undef_zero" ] || \
[ "$2" = "sat_si_def_undef" ] || \
[ "$2" = "sat_si_def_undef_zero" ]; then
expected_string="ERROR: The options -set-init-undef, -set-init-def, and -set-init-zero are exclusive!"
elif [ "$2" = "sat_failed_to_import_cell" ]; then
expected_string="ERROR: Failed to import cell "
elif [ "$2" = "sat_prove_skip_must_be_smaller_than_seq" ]; then
expected_string="ERROR: The value of -prove-skip must be smaller than the one of -seq."
elif [ "$2" = "sat_prove_and_tempinduct" ]; then
expected_string="ERROR: Options -prove-skip and -tempinduct don't work with each other. Use -seq instead of -prove-skip."
elif [ "$2" = "sat_got_tempinduct_but_nothing_to_prove" ]; then
expected_string="ERROR: Got -tempinduct but nothing to prove!"
elif [ "$2" = "sat_cant_perform_sat_on_empty_sel" ]; then
expected_string="ERROR: Can't perform SAT on an empty selection!"
elif [ "$2" = "sat_only_one_module_must_be_sel" ]; then
expected_string="ERROR: Only one module must be selected for the SAT pass! "
elif [ "$2" = "scc_expect1" ]; then
expected_string="ERROR: Found 0 SCCs but expected 1"
elif [ "$2" = "select_add_with_del" ] || \
[ "$2" = "select_assert_any_with_count" ] || \
[ "$2" = "select_assert_max_with_del" ] || \
[ "$2" = "select_assert_none_with_min" ]; then
expected_string="ERROR: Options -add, -del, -assert-none, -assert-any, assert-count, -assert-max or -assert-min can not be combined"
elif [ "$2" = "select_assert_any_failed" ]; then
expected_string="ERROR: Assertion failed: selection is empty: uuu"
elif [ "$2" = "select_assert_count_failed" ]; then
expected_string="ERROR: Assertion failed: selection contains 11 elements instead of the asserted 30: top"
elif [ "$2" = "select_assert_list_with_assert_max" ] || \
[ "$2" = "select_assert_list_with_del" ] || \
[ "$2" = "select_write_with_assert_count" ] || \
[ "$2" = "select_write_with_del" ] || \
[ "$2" = "select_count_with_assert_min" ] || \
[ "$2" = "select_count_with_assert_none" ]; then
expected_string="ERROR: Options -list, -write and -count can not be combined with -add, -del, -assert-none, -assert-any, assert-count, -assert-max, or -assert-min."
elif [ "$2" = "select_assert_max_failed" ]; then
expected_string="ERROR: Assertion failed: selection contains 11 elements, more than the maximum number 1: top"
elif [ "$2" = "select_assert_min_failed" ]; then
expected_string="ERROR: Assertion failed: selection contains 11 elements, less than the minimum number 30: top"
elif [ "$2" = "select_assert_none_failed" ]; then
expected_string="ERROR: Assertion failed: selection is not empty: top"
elif [ "$2" = "select_cant_open_for_reading" ]; then
expected_string="ERROR: Can't open 'txt.txt' for reading: No such file or directory"
elif [ "$2" = "select_cant_open_for_writing" ]; then
expected_string="ERROR: Can't open './tt/ot.txt' for writing: No such file or directory"
elif [ "$2" = "select_clear_with_other_opt" ]; then
expected_string="ERROR: Option -clear can not be combined with any other options."
elif [ "$2" = "select_error_in_expand_op" ]; then
expected_string="ERROR: Syntax error in expand operator '%x:'."
elif [ "$2" = "select_none_with_other_opt" ]; then
expected_string="ERROR: Option -none can not be combined with any other options."
elif [ "$2" = "select_no_sel_to_check_as_any" ] || \
[ "$2" = "select_no_sel_to_check_as_count" ] || \
[ "$2" = "select_no_sel_to_check_as_max" ] || \
[ "$2" = "select_no_sel_to_check_as_min" ] || \
[ "$2" = "select_no_sel_to_check_as_none" ]; then
expected_string="ERROR: No selection to check."
elif [ "$2" = "select_no_such_module" ]; then
expected_string="ERROR: No such module: x"
elif [ "$2" = "select_nothing_to_add" ]; then
expected_string="ERROR: Nothing to add to selection."
elif [ "$2" = "select_nothing_to_del" ]; then
expected_string="ERROR: Nothing to delete from selection."
elif [ "$2" = "select_one_elem_for__a" ] || \
[ "$2" = "select_one_elem_for__cie" ] || \
[ "$2" = "select_one_elem_for__ci" ] || \
[ "$2" = "select_one_elem_for__coe" ] || \
[ "$2" = "select_one_elem_for__co" ] || \
[ "$2" = "select_one_elem_for__C" ] || \
[ "$2" = "select_one_elem_for__c" ] || \
[ "$2" = "select_one_elem_for__m" ] || \
[ "$2" = "select_one_elem_for__M" ] || \
[ "$2" = "select_one_elem_for__n" ] || \
[ "$2" = "select_one_elem_for__R" ] || \
[ "$2" = "select_one_elem_for__s" ] || \
[ "$2" = "select_one_elem_for__xe" ] || \
[ "$2" = "select_one_elem_for__x" ]; then
expected_string="ERROR: Must have at least one element on the stack for operator"
elif [ "$2" = "select_one_elem_for__D" ] || \
[ "$2" = "select_one_elem_for__d" ] || \
[ "$2" = "select_one_elem_for__i" ] || \
[ "$2" = "select_one_elem_for__u" ]; then
expected_string="ERROR: Must have at least two elements on the stack for operator"
elif [ "$2" = "select_read_with_selection_expr" ]; then
expected_string="ERROR: Option -read can not be combined with a selection expression."
elif [ "$2" = "select_selection_isnt_defined" ]; then
expected_string="ERROR: Selection @ is not defined!"
elif [ "$2" = "select_set_with_assert_any" ] || \
[ "$2" = "select_set_with_assert_max" ] || \
[ "$2" = "select_set_with_count" ] || \
[ "$2" = "select_set_with_del" ] || \
[ "$2" = "select_set_with_list" ]; then
expected_string="ERROR: Option -set can not be combined with -list, -write, -count, -add, -del, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min."
elif [ "$2" = "select_unknown_opt" ]; then
expected_string="ERROR: Unknown option -x."
elif [ "$2" = "select_unknown_selection" ]; then
expected_string="ERROR: Unknown selection operator '%xmux'"
elif [ "$2" = "select_cd_invalid_number_of_args" ]; then
expected_string="ERROR: Invalid number of arguments."
elif [ "$2" = "select_cd_no_such_module" ]; then
expected_string="ERROR: No such module \`tt/tt' found!"
elif [ "$2" = "setattr_cant_decode_value" ]; then
expected_string="ERROR: Can't decode value "
elif [ "$2" = "setundef_expose_without_undriven" ]; then
expected_string="ERROR: Option -expose must be used with option -undriven."
elif [ "$2" = "setundef_init_with_anyconst" ] || \
[ "$2" = "setundef_init_with_anyseq" ]; then
expected_string="ERROR: The options -init and -anyseq / -anyconst are exclusive."
elif [ "$2" = "setundef_one_of_options" ]; then
expected_string="ERROR: One of the options -zero, -one, -anyseq, -anyconst, or -random <seed> must be specified."
elif [ "$2" = "setundef_undriven_with_process" ]; then
expected_string="ERROR: The 'setundef' command can't operate in -undriven mode on modules with processes. Run 'proc' first."
elif [ "$2" = "show_only_one_module" ]; then
expected_string="ERROR: For formats different than 'ps' or 'dot' only one module must be selected."
elif [ "$2" = "show_cant_open_dot_file" ]; then
expected_string="ERROR: Can't open dot file "
elif [ "$2" = "show_cant_open_lib_file" ]; then
expected_string="ERROR: Can't open lib file "
elif [ "$2" = "show_nothing_there_to_show" ]; then
expected_string="ERROR: Nothing there to show."
elif [ "$2" = "splice_port_and_no_port" ]; then
expected_string="ERROR: The options -port and -no_port are exclusive!"
elif [ "$2" = "splice_sel_by_cell_and_sel_any_bit" ]; then
expected_string="ERROR: The options -sel_by_cell and -sel_any_bit are exclusive!"
elif [ "$2" = "splice_sel_by_cell_and_sel_by_wire" ]; then
expected_string="ERROR: The options -sel_by_cell and -sel_by_wire are exclusive!"
elif [ "$2" = "stat_unsupported_tech" ]; then
expected_string="ERROR: Unsupported technology: "
elif [ "$2" = "stat_cant_find_module" ]; then
expected_string="ERROR: Can't find module"
elif [ "$2" = "stat_cant_open_lib_file" ]; then
expected_string="ERROR: Can't open liberty file "
elif [ "$2" = "tee_o_cant_create_file" ] || \
[ "$2" = "tee_a_cant_create_file" ]; then
expected_string="ERROR: Can't create file"
elif [ "$2" = "test_cell_failed_to_open" ]; then
expected_string="ERROR: Failed to open output file "
elif [ "$2" = "test_cell_unexpected_opt" ]; then
expected_string="ERROR: Unexpected option: "
elif [ "$2" = "test_cell_cell_type_not_supported" ]; then
expected_string="ERROR: The cell type \`\$_XOR_' is currently not supported. Try one of these:"
elif [ "$2" = "test_cell_no_cell_t_specified" ]; then
expected_string="ERROR: No cell type to test specified."
elif [ "$2" = "test_cell_dont_spec_cell_type_with_f" ]; then
expected_string="ERROR: Do not specify any cell types when using -f."
elif [ "$2" = "write_file_missing_name" ] || \
[ "$2" = "write_file_a_missing_name" ]; then
expected_string="ERROR: Missing output filename."
fi
if yosys -ql yosys.log ../../scripts/$2.ys; then
echo FAIL > ${1}_${2}.status
else
......
misc/sat_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
initial A = 0;
initial cout = 0;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/scc_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (x,y,o);
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/scripts/add_error.ys 0 → 100644
read_verilog ../top.v
add -input i 2
add -wire i 2
tee -o result.log dump
misc/scripts/bugpoint_do_not_crash.ys 0 → 100644
read_verilog ../top.v
tee -o result.log bugpoint -script ../script.ys -connections
misc/scripts/bugpoint_fully_selected_des.ys 0 → 100644
read_verilog ../top.v
select bb
tee -o result.log bugpoint -script ../script.ys
misc/scripts/bugpoint_grep_string_not_found.ys 0 → 100644
read_verilog ../top.v
tee -o result.log bugpoint -script ../script.ys -grep "SSS"
misc/scripts/bugpoint_missing_script.ys 0 → 100644
read_verilog ../top.v
tee -o result.log bugpoint
misc/scripts/check_error.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log check -assert
misc/scripts/check_initdrv.ys
read_verilog -sv ../top.v
read_verilog -sv ../top1.v
proc
tee -o result.log check -initdrv
misc/scripts/check_noinit.ys
read_verilog -sv ../top.v
read_verilog -sv ../top1.v
proc
tee -o result.log check -noinit
misc/scripts/chformal_error.ys 0 → 100644
read_verilog -sv ../top.v
chformal
tee -o result.log dump
misc/scripts/chparam_error.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log chparam -set X 2 -list top
misc/scripts/connect_cannot_parse_set_lhs_expr.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log connect -set sdf sdf
misc/scripts/connect_cannot_parse_set_rhs_expr.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log connect -set d sdf
misc/scripts/connect_cant_find_cell.ys 0 → 100644
read_verilog -sv ../top.v
proc
connect -set d q
tee -o result.log connect -port $procddff$2 D d
misc/scripts/connect_failed_parse_unset.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log connect -unset sdf
misc/scripts/connect_failed_to_parse_port_expr.ys 0 → 100644
read_verilog -sv ../top.v
proc
connect -set d q
tee -o result.log connect -port $procdff$2 D dd
misc/scripts/connect_found_process.ys 0 → 100644
read_verilog -sv ../top.v
tee -o result.log connect -unset d q
misc/scripts/connect_multiple_modules.ys 0 → 100644
read_verilog -sv ../top_2.v
proc
tee -o result.log connect -unset d q
misc/scripts/connect_no_modules.ys 0 → 100644
tee -o result.log connect -unset d q
misc/scripts/connect_opt_expected.ys 0 → 100644
read_verilog -sv ../top.v
proc
connect -set d q
tee -o result.log connect
misc/scripts/connect_port_with_nounset.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log connect -port $procdff$2 D d -nounset d
misc/scripts/connect_set_with_port.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log connect -set d q -port $procdff$2 D d
misc/scripts/connect_set_with_unset.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log connect -set d q -unset d
misc/scripts/connect_set_with_unset_and_port.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log connect -set d q -unset d -port $procdff$2 D d
misc/scripts/connect_unset_with_nounset.ys 0 → 100644
read_verilog -sv ../top.v
proc
connect -set d q
tee -o result.log connect -unset d -nounset d
misc/scripts/connect_unset_with_nounset_and_port.ys 0 → 100644
read_verilog -sv ../top.v
proc
connect -set d q
tee -o result.log connect -unset d -port $procdff$2 D d -nounset d
misc/scripts/connect_unset_with_port.ys 0 → 100644
read_verilog -sv ../top.v
proc
connect -set d q
tee -o result.log connect -unset d -port $procdff$2 D d
misc/scripts/cover_cant_create_file.ys 0 → 100644
read_verilog ../top.v
tee -o result.log cover -o aa/out.txt
misc/scripts/design_no_pushed_design.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log design -pop
misc/scripts/design_no_saved_design_copy_from.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log design -copy-from first -as top_2 top
misc/scripts/design_no_saved_design_import.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log design -import first top
misc/scripts/design_no_saved_design_load.ys 0 → 100644
read_verilog -sv ../top.v
proc
design -load first
misc/scripts/design_no_top_module.ys 0 → 100644
read_verilog -sv ../top.v
design -save first
tee -o result.log design -import first
misc/scripts/eval_cant_find_input.ys 0 → 100644
read_verilog ../top_err_1.v
tee -o result.log eval -vloghammer_report mid dle s 1
misc/scripts/eval_cant_find_mod_1.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -brute_force_equiv_checker u top
misc/scripts/eval_cant_find_mod_2.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -brute_force_equiv_checker top u
misc/scripts/eval_cant_find_mod_in_curr_des.ys 0 → 100644
read_verilog ../top.v
tee -o result.log eval -vloghammer_report middle dle x 1
misc/scripts/eval_cant_find_mod_in_curr_dess.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -vloghammer_report mid dle x 1
misc/scripts/eval_diff_lhs_rhs_sizes.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -set x 1 -set y 2'b11 u_rtl
misc/scripts/eval_empty_selection.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval u
misc/scripts/eval_failed_to_parse_lhs.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -set u 0 middle
misc/scripts/eval_failed_to_parse_pattern.ys 0 → 100644
read_verilog ../top.v
tee -o result.log eval -vloghammer_report mid dle x d
misc/scripts/eval_failed_to_parse_rhs.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -set x u middle
misc/scripts/eval_failed_to_parse_show_expr.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -show u middle
misc/scripts/eval_failed_to_parse_table_expr.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -table u middle
misc/scripts/eval_has_no_counterpart.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -brute_force_equiv_checker top u_rtl
misc/scripts/eval_mods_arent_equiv.ys 0 → 100644
read_verilog ../top_err_1.v
proc
tee -o result.log eval -brute_force_equiv_checker middle u_rtl
misc/scripts/eval_no_output_wire.ys 0 → 100644
read_verilog ../top_err_1.v
tee -o result.log eval -vloghammer_report mid dle x 1
misc/scripts/eval_only_one_module.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval
misc/scripts/eval_pattern_is_to_short.ys 0 → 100644
read_verilog ../top_err_2.v
tee -o result.log eval -vloghammer_report mid dle x 1'b1
misc/scripts/eval_port_doesnt_match.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -brute_force_equiv_checker u_rtl top
misc/scripts/eval_rhs_expr.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log eval -set x 1 -set y x u_rtl
misc/scripts/eval_two_distinct_solutions.ys 0 → 100644
read_verilog ../top_err_3.v
tee -o result.log eval -vloghammer_report u_ rtl x 1'b1
misc/scripts/eval_wire_isnt_an_input.ys 0 → 100644
read_verilog ../top.v
tee -o result.log eval -vloghammer_report mid dle w 1
misc/scripts/fmcombine_gate_cell_not_found.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log fmcombine top u_mid1 u_mid8
misc/scripts/fmcombine_gold_cell_not_found.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log fmcombine top u_mid8 u_mid3
misc/scripts/fmcombine_invalid_number_of_param.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log fmcombine
misc/scripts/fmcombine_module_not_found.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log fmcombine topp u_mid1 u_mid3
misc/scripts/fmcombine_nop_with_bwd.ys 0 → 100644
read_verilog ../top.v
tee -o result.log fmcombine -nop -bwd top u_mid1 u_mid2
misc/scripts/fmcombine_nop_with_fwd.ys 0 → 100644
read_verilog ../top.v
tee -o result.log fmcombine -nop -fwd top u_mid1 u_mid2
misc/scripts/fmcombine_nop_with_fwd_bwd.ys 0 → 100644
read_verilog ../top.v
tee -o result.log fmcombine -nop -fwd -bwd top u_mid1 u_mid2
misc/scripts/fmcombine_types_not_match.ys 0 → 100644
read_verilog ../top_err_1.v
proc
tee -o result.log fmcombine top u_mid1 u_urtl
misc/scripts/freduce_logic_loop.ys 0 → 100644
read_verilog ../top_err_1.v
tee -o result.log freduce
proc
tee -o result.log freduce
synth
tee -o result.log freduce
misc/scripts/miter_cant_find_gate_module.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log miter -equiv top gate top
misc/scripts/miter_cant_find_gold_module.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log miter -equiv gold gate top
misc/scripts/miter_cant_find_module.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log miter -assert t
misc/scripts/miter_missing_mode_param.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log miter
misc/scripts/miter_no_match_in_gate.ys 0 → 100644
read_verilog -sv ../top_err_1.v
proc
tee -o result.log miter -equiv middle u_rtl top1
misc/scripts/miter_no_match_in_gold.ys 0 → 100644
read_verilog -sv ../top_err_1.v
proc
tee -o result.log miter -equiv u_rtl middle top1
misc/scripts/miter_there_is_already_a_module.ys 0 → 100644
read_verilog -sv ../top.v
proc
tee -o result.log miter -equiv top middle top
misc/scripts/mutate_error.ys 0 → 100644
read_verilog ../top.v
tee -o result.log mutate -cell $add$../top.v:12$1 -port \Y -portbit 0 -ctrlbit 0 -module top
misc/scripts/plugin_error.ys 0 → 100644
read_verilog ../top.v
tee -o result.log plugin -l
plugin -i uu -a alias
tee -o result.log plugin -l
misc/scripts/rename_invalid_number_of_args.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log rename
misc/scripts/rename_invalid_number_of_args_top.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log rename -top
misc/scripts/rename_mode_out_requires.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log rename -output u uu
misc/scripts/rename_no_top_module.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log rename -top top
misc/scripts/rename_obj_not_found.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log rename u uu
misc/scripts/sat_all_with_tempinduct.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -all -prove x 1 -tempinduct middle
misc/scripts/sat_cant_open_json_file.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -dump_json dir/out.json middle
misc/scripts/sat_cant_open_vcd_file.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -dump_vcd dir/out.vcd middle
misc/scripts/sat_cnf_open_json_file.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -dump_cnf dir/out.cnf middle
misc/scripts/sat_failed_to_import_cell.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -prove-skip 1 -prove x 1 -seq 2 top
misc/scripts/sat_falsify_fail.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -falsify middle
misc/scripts/sat_got_tempinduct_but_nothing_to_prove.ys 0 → 100644
read_verilog ../top.v
tee -o result.log sat -tempinduct middle
misc/scripts/sat_max_all_with_tempinduct.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -max 5 -all -prove x 1 -tempinduct middle
misc/scripts/sat_max_max_undef_with_tempinduct.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -max_undef -all -prove x 1 -tempinduct top
misc/scripts/sat_max_maxundef_all_with_tempinduct.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -max 1 -max_undef -all -prove x 1 -tempinduct top
misc/scripts/sat_max_maxundef_with_tempinduct.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -max 1 -max_undef -prove x 1 -tempinduct top
misc/scripts/sat_max_with_tempinduct.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -max 1 -prove x 1 -tempinduct top
misc/scripts/sat_maxsteps_only_for_tempinduct.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -maxsteps 3 middle
misc/scripts/sat_maxundef_with_tempinduct.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -max_undef -prove x 1 -tempinduct top
misc/scripts/sat_only_one_module_must_be_sel.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat
misc/scripts/sat_prove_and_tempinduct.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -prove-skip 365 -prove x 1 -tempinduct top
misc/scripts/sat_prove_diff_size.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -prove x 2'b11 middle
misc/scripts/sat_prove_lhs_fail.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -prove X 0 middle
misc/scripts/sat_prove_rhs_fail.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -prove x X middle
misc/scripts/sat_prove_skip_must_be_smaller_than_seq.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -prove-skip 365 -prove x 1 -seq 1 top
misc/scripts/sat_provex_diff_size.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -prove-x x 2'b11 middle
misc/scripts/sat_provex_lhs_fail.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -prove-x X 0 middle
misc/scripts/sat_provex_rhs_fail.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -prove-x x X middle
misc/scripts/sat_set_all_undef_at_fail.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -set-all-undef-at U 1 middle
misc/scripts/sat_set_all_undef_fail.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -set-all-undef U middle
misc/scripts/sat_set_any_undef_at_fail.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -set-any-undef-at U middle
misc/scripts/sat_set_any_undef_fail.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -set-any-undef U middle
misc/scripts/sat_set_at_diff_size.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -set-at x 2'b11 middle
misc/scripts/sat_set_at_lhs_fail.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -set-at X 0 middle
misc/scripts/sat_set_at_rhs_fail.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -set-at x X middle
misc/scripts/sat_set_def_at_fail.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -set-def-at U middle
misc/scripts/sat_set_def_fail.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -set-def U middle
misc/scripts/sat_set_diff_size.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -set x 2'b11 middle
misc/scripts/sat_set_lhs_fail.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -set X 0 middle
misc/scripts/sat_set_rhs_fail.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -set x X middle
misc/scripts/sat_show_fail.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -show X middle
misc/scripts/sat_si_def_undef.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -set-init-undef -set-init-def middle
misc/scripts/sat_si_def_undef_zero.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -set-init-undef -set-init-def -set-init-zero middle
misc/scripts/sat_si_def_zero.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -set-init-def -set-init-zero middle
misc/scripts/sat_si_undef_zero.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -set-init-undef -set-init-zero middle
misc/scripts/sat_unset_at_fail.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -unset-at U middle
misc/scripts/sat_verify_fail.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sat -verify -prove x 1 -tempinduct middle
misc/scripts/select_add_with_del.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -add -del
tee -o result.log select -list
misc/scripts/select_assert_any_failed.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -assert-any uuu
tee -o result.log select -list
misc/scripts/select_assert_any_with_count.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -assert-any -assert-count 3 top
tee -o result.log select -list
misc/scripts/select_assert_count_failed.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -assert-count 30 top
tee -o result.log select -list
misc/scripts/select_assert_list_with_assert_max.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -list -assert-max 3 top
tee -o result.log select -list
misc/scripts/select_assert_list_with_del.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -list -del
tee -o result.log select -list
misc/scripts/select_assert_max_failed.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -assert-max 1 top
tee -o result.log select -list
misc/scripts/select_assert_max_with_del.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -del -assert-max 3 top
tee -o result.log select -list
misc/scripts/select_assert_min_failed.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -assert-min 30 top
tee -o result.log select -list
misc/scripts/select_assert_none_failed.ys 0 → 100644
read_verilog ../top.v
proc
select *
tee -o result.log select -assert-none top
tee -o result.log select -list
misc/scripts/select_assert_none_with_min.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -assert-none -assert-min 3 top
tee -o result.log select -list
misc/scripts/select_cant_open_for_reading.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -read txt.txt
tee -o result.log select -list
misc/scripts/select_cant_open_for_writing.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -write ./tt/ot.txt
tee -o result.log select -list
misc/scripts/select_cd_invalid_number_of_args.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log cd sdf dfsf
misc/scripts/select_cd_no_such_module.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log cd tt/tt
misc/scripts/select_clear_with_other_opt.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select */t:$mux %x:+[A] */t:$mux %D -clear
tee -o result.log select -list
misc/scripts/select_count_with_assert_min.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -count 11 -assert-min 33 top
tee -o result.log select -list
misc/scripts/select_count_with_assert_none.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -assert-none -count 3 top
tee -o result.log select -list
misc/scripts/select_error_in_expand_op.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select select */t:$mux %x: */t:$mux %d
tee -o result.log select -list
misc/scripts/select_no_sel_to_check_as_any.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -assert-any
tee -o result.log select -list
misc/scripts/select_no_sel_to_check_as_count.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -assert-count 3
tee -o result.log select -list
misc/scripts/select_no_sel_to_check_as_max.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -assert-max 3
tee -o result.log select -list
misc/scripts/select_no_sel_to_check_as_min.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -assert-min 3
tee -o result.log select -list
misc/scripts/select_no_sel_to_check_as_none.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -assert-none
tee -o result.log select -list
misc/scripts/select_no_such_module.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -module x
tee -o result.log select -list
misc/scripts/select_none_with_other_opt.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select */t:$mux %x:+[A] */t:$mux %D -none
tee -o result.log select -list
misc/scripts/select_nothing_to_add.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -add
tee -o result.log select -list
misc/scripts/select_nothing_to_del.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -del
tee -o result.log select -list
misc/scripts/select_one_elem_for__C.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select %C
tee -o result.log select -list
misc/scripts/select_one_elem_for__D.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select %D
tee -o result.log select -list
misc/scripts/select_one_elem_for__M.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select %M
tee -o result.log select -list
misc/scripts/select_one_elem_for__R.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select %R
tee -o result.log select -list
misc/scripts/select_one_elem_for__a.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select %a
tee -o result.log select -list
misc/scripts/select_one_elem_for__c.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select %c
tee -o result.log select -list
misc/scripts/select_one_elem_for__ci.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select %ci
tee -o result.log select -list
misc/scripts/select_one_elem_for__cie.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select %cie
tee -o result.log select -list
misc/scripts/select_one_elem_for__co.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select %co
tee -o result.log select -list
misc/scripts/select_one_elem_for__coe.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select %coe
tee -o result.log select -list
misc/scripts/select_one_elem_for__d.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select %d
tee -o result.log select -list
misc/scripts/select_one_elem_for__i.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select %i
tee -o result.log select -list
misc/scripts/select_one_elem_for__m.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select %m
tee -o result.log select -list
misc/scripts/select_one_elem_for__n.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select %n
tee -o result.log select -list
misc/scripts/select_one_elem_for__s.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select %s
tee -o result.log select -list
misc/scripts/select_one_elem_for__u.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select %u
tee -o result.log select -list
misc/scripts/select_one_elem_for__x.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select %x */t %d
tee -o result.log select -list
misc/scripts/select_one_elem_for__xe.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select %xe
tee -o result.log select -list
misc/scripts/select_read_with_selection_expr.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -read -add x:o
tee -o result.log select -list
misc/scripts/select_selection_isnt_defined.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select @
tee -o result.log select -list
misc/scripts/select_set_with_assert_any.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -set aa -assert-any top
tee -o result.log select -list
misc/scripts/select_set_with_assert_max.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -set a -assert-max 2 top
tee -o result.log select -list
misc/scripts/select_set_with_count.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -set a -assert-count 3 top
tee -o result.log select -list
misc/scripts/select_set_with_del.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -set a -del a
tee -o result.log select -list
misc/scripts/select_set_with_list.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -set a -list
tee -o result.log select -list
misc/scripts/select_unknown_opt.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -x
tee -o result.log select -list
misc/scripts/select_unknown_selection.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select */t:$mux %xmux */t:$mux %d
tee -o result.log select -list
misc/scripts/select_write_with_assert_count.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -write out.txt -assert-count 4 top
tee -o result.log select -list
misc/scripts/select_write_with_del.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log select -write out.txt -del
tee -o result.log select -list
misc/scripts/setattr_cant_decode_value.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log setattr -set a af*&
misc/scripts/setundef_expose_without_undriven.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log setundef -expose
misc/scripts/setundef_init_with_anyconst.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log setundef -init -anyconst
misc/scripts/setundef_init_with_anyseq.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log setundef -init -anyseq
misc/scripts/setundef_one_of_options.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log setundef -random 256 -zero -one -anyseq -anyconst
misc/scripts/setundef_undriven_with_process.ys 0 → 100644
read_verilog ../top.v
tee -o result.log setundef -undriven
misc/scripts/show_cant_open_dot_file.ys 0 → 100644
read_verilog ../top.v
tee -o result.log show -format dot -prefix tt/tt
misc/scripts/show_cant_open_lib_file.ys 0 → 100644
read_verilog ../top.v
tee -o result.log show -lib l.lib top
misc/scripts/show_nothing_there_to_show.ys 0 → 100644
tee -o result.log show dot.dot top
misc/scripts/show_only_one_module.ys 0 → 100644
read_verilog ../top.v
tee -o result.log show -format svg
misc/scripts/splice_port_and_no_port.ys 0 → 100644
read_verilog ../top.v
synth
splice -port WR_EN -no_port q_b
tee -o result.log dump
misc/scripts/splice_sel_by_cell_and_sel_any_bit.ys 0 → 100644
read_verilog ../top.v
synth
splice -sel_by_cell -sel_any_bit
tee -o result.log dump
misc/scripts/splice_sel_by_cell_and_sel_by_wire.ys 0 → 100644
read_verilog ../top.v
synth
splice -sel_by_cell -sel_by_wire
tee -o result.log dump
misc/scripts/stat_cant_find_module.ys 0 → 100644
read_verilog ../top.v
synth -top top
tee -o result.log stat -top uut
misc/scripts/stat_cant_open_lib_file.ys 0 → 100644
read_verilog ../top.v
tee -o result.log stat -liberty lib.lib
misc/scripts/stat_unsupported_tech.ys 0 → 100644
read_verilog ../top.v
synth_xilinx
tee -o result.log stat -tech ice40
misc/scripts/tee_a_cant_create_file.ys 0 → 100644
read_verilog ../top.v
proc
tee -a ./tt/result.log ls
misc/scripts/tee_o_cant_create_file.ys 0 → 100644
read_verilog ../top.v
proc
tee -o ./tt/result.log ls
misc/scripts/test_cell_cell_type_not_supported.ys 0 → 100644
read_verilog ../top.v
synth -top top
tee -o result.log test_cell $_XOR_
misc/scripts/test_cell_dont_spec_cell_type_with_f.ys 0 → 100644
read_verilog ../gold.v
synth -top gold
write_ilang ilang.ilang
design -reset
tee -o result.log test_cell -f ilang.ilang $add
misc/scripts/test_cell_failed_to_open.ys 0 → 100644
read_verilog ../top.v
synth -top top
tee -o result.log test_cell -vlog tt/vlog.v
misc/scripts/test_cell_no_cell_t_specified.ys 0 → 100644
read_verilog ../top.v
synth -top top
tee -o result.log test_cell
misc/scripts/test_cell_unexpected_opt.ys 0 → 100644
read_verilog ../top.v
synth -top top
tee -o result.log test_cell -scd
misc/scripts/write_file_a_missing_name.ys 0 → 100644
read_verilog ../top.v
tee -o result.log write_file -a
misc/scripts/write_file_missing_name.ys 0 → 100644
read_verilog ../top.v
tee -o result.log write_file
misc/select_cd_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (x,y,o);
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/select_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (x,y,o);
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/setattr_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (x,y,o);
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/setundef_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
//assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/show_error/lib.lib 0 → 100644
library (Cell_EX2) {
technology (cmos);
delay_model : table_lookup;
capacitive_load_unit (1,pf);
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1A";
default_fanout_load : 0.0;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
input_threshold_pct_rise : 50.0;
input_threshold_pct_fall : 50.0;
output_threshold_pct_rise : 50.0;
output_threshold_pct_fall : 50.0;
slew_lower_threshold_pct_fall : 10.0;
slew_lower_threshold_pct_rise : 10.0;
slew_upper_threshold_pct_fall : 90.0;
slew_upper_threshold_pct_rise : 90.0;
lu_table_template (delay_template4x4) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1,2,3,4");
index_2 ("1,2,3,4");
}
cell (top) {
area : 2;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00376;
rise_capacitance : 0.00376;
fall_capacitance : 0.00377;
rise_capacitance_range (0.00376 , 0.00376) ;
fall_capacitance_range (0.00377 , 0.00377) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.08000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
cell (INVX2) {
area : 3;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00676;
rise_capacitance : 0.00676;
fall_capacitance : 0.00677;
rise_capacitance_range (0.00676 , 0.00676) ;
fall_capacitance_range (0.00677 , 0.00677) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.16000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
}
misc/show_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (x,y,o);
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/show_error/top_err_1.v 0 → 100644
module top
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/splice_error/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
misc/stat_error/lib.lib 0 → 100644
library (Cell_EX2) {
technology (cmos);
delay_model : table_lookup;
capacitive_load_unit (1,pf);
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1A";
default_fanout_load : 0.0;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
input_threshold_pct_rise : 50.0;
input_threshold_pct_fall : 50.0;
output_threshold_pct_rise : 50.0;
output_threshold_pct_fall : 50.0;
slew_lower_threshold_pct_fall : 10.0;
slew_lower_threshold_pct_rise : 10.0;
slew_upper_threshold_pct_fall : 90.0;
slew_upper_threshold_pct_rise : 90.0;
lu_table_template (delay_template4x4) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1,2,3,4");
index_2 ("1,2,3,4");
}
cell (top) {
area : 2;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00376;
rise_capacitance : 0.00376;
fall_capacitance : 0.00377;
rise_capacitance_range (0.00376 , 0.00376) ;
fall_capacitance_range (0.00377 , 0.00377) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.08000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
cell (INVX2) {
area : 3;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00676;
rise_capacitance : 0.00676;
fall_capacitance : 0.00677;
rise_capacitance_range (0.00676 , 0.00676) ;
fall_capacitance_range (0.00677 , 0.00677) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.16000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
}
misc/stat_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (x,y,o);
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/tee_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (x,y,o);
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/test_cell_error/gold.v 0 → 100644
module gold
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
misc/test_cell_error/ilang.ilang 0 → 100644
# Generated by Yosys 0.8+492 (git sha1 2058c7c5, gcc 8.3.0-6ubuntu1~18.10 -Og -fPIC)
autoidx 169
attribute \top 1
attribute \src "gold.v:1"
module \gold
wire $abc$163$new_n6_
wire $abc$163$new_n7_
wire $abc$163$new_n9_
attribute \src "gold.v:7"
wire output 4 \A
attribute \src "gold.v:5"
wire input 3 \cin
attribute \src "gold.v:8"
wire output 5 \cout
attribute \src "gold.v:3"
wire input 1 \x
attribute \src "gold.v:4"
wire input 2 \y
cell $_NOT_ $abc$163$auto$blifparse.cc:371:parse_blif$164
connect \A \y
connect \Y $abc$163$new_n6_
end
cell $_XNOR_ $abc$163$auto$blifparse.cc:371:parse_blif$165
connect \A \cin
connect \B \x
connect \Y $abc$163$new_n7_
end
cell $_XOR_ $abc$163$auto$blifparse.cc:371:parse_blif$166
connect \A $abc$163$new_n7_
connect \B $abc$163$new_n6_
connect \Y \A
end
cell $_NAND_ $abc$163$auto$blifparse.cc:371:parse_blif$167
connect \A \cin
connect \B \x
connect \Y $abc$163$new_n9_
end
cell $_OAI3_ $abc$163$auto$blifparse.cc:371:parse_blif$168
connect \A $abc$163$new_n7_
connect \B $abc$163$new_n6_
connect \C $abc$163$new_n9_
connect \Y \cout
end
end
misc/test_cell_error/simlib.v 0 → 100644
module \$add (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) + $signed(B);
end else begin:BLOCK2
assign Y = A + B;
end
endgenerate
endmodule
misc/test_cell_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
misc/write_file_error/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
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