Commit 14411dc7 by Eddie Hung

Be really sure test is run

parent fdc77d04
......@@ -47,7 +47,7 @@ for fn in glob.glob('*.v'):
assert_area = ['select t:{0} -assert-count {1}'.format(r,v*W) for r,v in zip(['LUT1','LUT2','LUT3','LUT4','LUT5','LUT6','MUXF7','MUXF8'], area[N])]
print('''
`ifndef _AUTOTB
module \$__test ;
module __test ;
wire [4095:0] assert_area = "%s";
endmodule
`endif
......
......@@ -24,5 +24,9 @@ python3 generate_small.py
python3 generate_large.py
python3 ../assert_area.py
${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="\
-p 'synth_xilinx -abc9 -widemux 5; script -select \$__test/w:assert_area'\
-p 'design -copy-to __test __test; \
synth_xilinx -abc9 -widemux 5; \
design -copy-from __test *; \
select -assert-any __test; \
script -select __test/w:assert_area'\
-l ../../../../../techlibs/xilinx/cells_sim.v"
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