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lvzhengyang
yosys-tests
Commits
13db188d
Commit
13db188d
authored
Jul 16, 2019
by
Eddie Hung
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Remove exit 1 as per @mmicko
parent
7da2877d
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bigsim/run.sh
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bigsim/run.sh
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13db188d
...
...
@@ -68,20 +68,18 @@ $iverilog_cmd
if
[
$?
!=
0
]
;
then
echo
FAIL
>
${
1
}
_
${
2
}
.status
touch .stamp
exit
1
exit
0
fi
vvp
-N
sim
$PLUSARGS
| pv
-l
>
output.txt
if
[
$?
!=
0
]
;
then
echo
FAIL
>
${
1
}
_
${
2
}
.status
touch .stamp
exit
1
fi
if
[
"
$2
"
=
"falsify"
]
;
then
if
cmp output.txt ../work_sim/output.txt
;
then
echo
FAIL
>
../../
${
1
}
_
${
2
}
.status
exit
1
else
echo
PASS
>
../../
${
1
}
_
${
2
}
.status
fi
...
...
@@ -90,7 +88,6 @@ elif [ "$2" != "sim" ]; then
echo
PASS
>
../../
${
1
}
_
${
2
}
.status
else
echo
FAIL
>
../../
${
1
}
_
${
2
}
.status
exit
1
fi
elif
[
"
$2
"
==
"sim"
]
;
then
echo
PASS
>
../../
${
1
}
_
${
2
}
.status
...
...
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