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yosys-tests
Commit 12b1e247 by Eddie Hung
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Merge remote-tracking branch 'origin/master' into xc7srl_cleanup

parents 73791bae 823bc5ba
Showing with 285 additions and 7 deletions
architecture/run.sh
...@@ -22,7 +22,7 @@ if echo "$1" | grep ".*_error"; then ...@@ -22,7 +22,7 @@ if echo "$1" | grep ".*_error"; then
elif [ "$2" = "synth_intel_invalid_family" ]; then elif [ "$2" = "synth_intel_invalid_family" ]; then
expected_string="ERROR: Invalid or not family specified" expected_string="ERROR: Invalid or not family specified"
elif [ "$2" = "synth_xilinx_invalid_arch" ]; then elif [ "$2" = "synth_xilinx_invalid_arch" ]; then
expected_string="ERROR: Invalid Xilinx -arch setting: " expected_string="ERROR: Invalid Xilinx -family setting: "
fi fi
......
frontends/read_aiger_ff/testbench.v
...@@ -22,10 +22,10 @@ module testbench; ...@@ -22,10 +22,10 @@ module testbench;
top uut ( top uut (
.clk (clk ), .clk (clk ),
.n1 (n1 ), .__1__ (n1 ),
.n2 (n2 ), .__2__ (n2 ),
.n3 (n3 ), .__3__ (n3 ),
.n3_inv (n3_inv ) .__3b__ (n3_inv )
); );
always @(posedge clk) begin always @(posedge clk) begin
......
frontends/read_aiger_latch/testbench.v
...@@ -21,8 +21,8 @@ module testbench; ...@@ -21,8 +21,8 @@ module testbench;
top uut ( top uut (
.clk (en ), .clk (en ),
//.n1 (dinA ), //.__1__ (dinA ),
.n1_inv (doutB ) .__1b__ (doutB )
); );
always @(posedge en) begin always @(posedge en) begin
......
misc/Makefile
...@@ -228,5 +228,7 @@ $(eval $(call template,fmcombine_error, fmcombine_invalid_number_of_param fmcomb ...@@ -228,5 +228,7 @@ $(eval $(call template,fmcombine_error, fmcombine_invalid_number_of_param fmcomb
#pmuxtree #pmuxtree
$(eval $(call template,pmuxtree, pmuxtree)) $(eval $(call template,pmuxtree, pmuxtree))
#opt_rmdff_sat
$(eval $(call template,opt_rmdff_sat, opt_rmdff_sat))
.PHONY: all clean .PHONY: all clean
misc/opt_rmdff_sat/bc.v 0 → 100644
module bc #(
parameter SIZE=2,
parameter WIDTH=16
)
(
input clk,
input rst,
output wire din_ready,
input wire din_valid,
input wire [WIDTH-1:0] din_data,
input wire [SIZE-1:0] dout_ready,
output wire [SIZE-1:0] dout_valid,
output wire [WIDTH*SIZE-1:0] dout_data
);
reg [SIZE-1 : 0] ready_reg;
wire [SIZE-1 : 0] ready_all;
genvar i;
initial begin
ready_reg = 0;
end
generate
for (i = 0; i < SIZE; i=i+1) begin
assign ready_all[i] = dout_ready[i] | ready_reg[i];
assign dout_valid[i] = din_valid & !ready_reg[i];
assign dout_data[(i+1)*WIDTH-1:i*WIDTH] = din_data;
always @(posedge clk) begin
if (rst || (!din_valid) || din_ready) begin
ready_reg[i] <= 1'b0;
end else if (dout_ready[i]) begin
ready_reg[i] <= 1'b1;
end
end
end
endgenerate
assign din_ready = &ready_all;
endmodule
misc/opt_rmdff_sat/demux.v 0 → 100644
module demux
(
input clk,
input rst,
output reg din_ready,
input wire din_valid,
input wire [2:0] din_data,
input wire dout0_ready,
output reg dout0_valid,
output wire [0:0] dout0_data,
input wire dout1_ready,
output reg dout1_valid,
output wire [1:0] dout1_data
);
wire [2:0] din_s; // u1 | u2
wire [1:0] din_s_data; // u2
assign din_s_data = din_s[1:0];
wire [0:0] din_s_ctrl; // u1
assign din_s_ctrl = din_s[2:2];
assign din_s = din_data;
assign dout0_data = din_data;
assign dout1_data = din_data;
always @*
begin
din_ready = 1'bx;
dout0_valid = 0;
dout1_valid = 0;
if (din_valid) begin
case(din_s_ctrl)
0 : begin
din_ready = dout0_ready;
dout0_valid = din_valid;
end
1 : begin
din_ready = dout1_ready;
dout1_valid = din_valid;
end
default: begin
din_ready = 1'bx;
dout0_valid = 1'bx;
dout1_valid = 1'bx;
end
endcase
end
end
endmodule
misc/opt_rmdff_sat/mux.v 0 → 100644
module mux
(
input clk,
input rst,
output reg ctrl_ready,
input wire ctrl_valid,
input wire [0:0] ctrl_data,
output reg din0_ready,
input wire din0_valid,
input wire [0:0] din0_data,
output reg din1_ready,
input wire din1_valid,
input wire [1:0] din1_data,
input wire dout_ready,
output reg dout_valid,
output wire [2:0] dout_data
);
wire [0:0] ctrl_s; // u1
wire [0:0] din0_s; // u1
wire [1:0] din1_s; // u2
reg [2:0] dout_s; // u1 | u2
reg [1:0] dout_s_data; // u2
assign dout_s[1:0] = dout_s_data;
reg [0:0] dout_s_ctrl; // u1
assign dout_s[2:2] = dout_s_ctrl;
assign ctrl_s = ctrl_data;
assign din0_s = din0_data;
assign din1_s = din1_data;
assign dout_data = dout_s;
wire handshake;
reg din_valid_sel;
assign handshake = dout_valid && dout_ready;
always @*
begin
din0_ready = din0_valid ? 0 : dout_ready;
din1_ready = din1_valid ? 0 : dout_ready;
dout_s_data = { 2 {1'bx}};
din_valid_sel = 0;
if (ctrl_valid) begin
case( ctrl_data )
0 : begin
din_valid_sel = din0_valid;
dout_s_data[0:0] = din0_s;
din0_ready = din0_valid ? handshake : dout_ready;
end
1 : begin
din_valid_sel = din1_valid;
dout_s_data[1:0] = din1_s;
din1_ready = din1_valid ? handshake : dout_ready;
end
default: begin
din0_ready = dout_ready;
din1_ready = dout_ready;
din_valid_sel = 1'bx;
end
endcase
end
end
assign ctrl_ready = ctrl_valid ? handshake : dout_ready;
assign dout_s_ctrl = ctrl_s;
assign dout_valid = ctrl_valid && din_valid_sel;
endmodule
\ No newline at end of file
misc/opt_rmdff_sat/top.v 0 → 100644
module top(
input clk,
input rst,
output wire din_ready,
input wire din_valid,
input wire [2:0] din_data,
input wire dout_ready,
output wire dout_valid,
output wire [2:0] dout_data
);
wire dout1_ready;
wire dout1_valid;
wire [0:0] dout1_data;
wire dout2_ready;
wire dout2_valid;
wire [1:0] dout2_data;
wire [1:0] din_bc_ready;
wire [1:0] din_bc_valid;
wire [5:0] din_bc_data;
bc #(
.SIZE(2'd2),
.WIDTH(2'd3)
)
bc_din (
.clk(clk),
.rst(rst),
.din_valid(din_valid),
.din_ready(din_ready),
.din_data(din_data),
.dout_valid(din_bc_valid),
.dout_ready(din_bc_ready),
.dout_data(din_bc_data)
);
demux demux (
.clk(clk),
.rst(rst),
.din_valid(din_bc_valid[0]),
.din_ready(din_bc_ready[0]),
.din_data(din_bc_data[2:0]),
.dout0_valid(dout1_valid),
.dout0_ready(dout1_ready),
.dout0_data(dout1_data),
.dout1_valid(dout2_valid),
.dout1_ready(dout2_ready),
.dout1_data(dout2_data)
);
mux mux (
.clk(clk),
.rst(rst),
.ctrl_valid(din_bc_valid[1]),
.ctrl_ready(din_bc_ready[1]),
.ctrl_data(din_bc_data[2]),
.din0_valid(dout1_valid),
.din0_ready(dout1_ready),
.din0_data(dout1_data),
.din1_valid(dout2_valid),
.din1_ready(dout2_ready),
.din1_data(dout2_data),
.dout_valid(dout_valid),
.dout_ready(dout_ready),
.dout_data(dout_data)
);
endmodule
misc/scripts/opt_rmdff_sat.ys 0 → 100644
read_verilog ../top.v
read_verilog ../bc.v
read_verilog ../demux.v
read_verilog ../mux.v
prep -flatten
opt_rmdff -sat
synth
tee -o result.log select -assert-count 0 t:$_DFF_P_
simple/scripts/synth_error.ys 0 → 100644
read_verilog ../top.v
select adff
synth
write_verilog synth.v
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