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yosys-tests
Commit 10d55221 by SergeyDegtyar
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Review and update tests for issues 444-644

parent 45c0ea8c
Showing with 75 additions and 578 deletions
regression/Makefile
......@@ -20,63 +20,6 @@ endef
#issue_00790
$(eval $(call template,issue_00790,issue_00790))
#issue_00444
$(eval $(call template,issue_00444,issue_00444))
#issue_00449
$(eval $(call template,issue_00449,issue_00449))
#issue_00457
$(eval $(call template,issue_00457,issue_00457))
#issue_00474
$(eval $(call template,issue_00474,issue_00474))
#issue_00481
$(eval $(call template,issue_00481,issue_00481))
#issue_00502
$(eval $(call template,issue_00502,issue_00502))
#issue_00524
$(eval $(call template,issue_00524,issue_00524))
#issue_00527
$(eval $(call template,issue_00527,issue_00527))
#issue_00567
$(eval $(call template,issue_00567,issue_00567))
#issue_00582
$(eval $(call template,issue_00582,issue_00582))
#issue_00589
$(eval $(call template,issue_00589,issue_00589))
#issue_00594
$(eval $(call template,issue_00594,issue_00594))
#issue_00603
$(eval $(call template,issue_00603,issue_00603))
#issue_00628
$(eval $(call template,issue_00628,issue_00628))
#issue_00630
$(eval $(call template,issue_00630,issue_00630))
#issue_00635
$(eval $(call template,issue_00635,issue_00635))
#issue_00639
$(eval $(call template,issue_00639,issue_00639))
#issue_00642
$(eval $(call template,issue_00642,issue_00642))
#issue_00644
$(eval $(call template,issue_00644,issue_00644))
#issue_00655
$(eval $(call template,issue_00655,issue_00655))
......@@ -311,9 +254,6 @@ $(eval $(call template,issue_01372,issue_01372))
#Still open bugs (should be failed):
#issue_00623
$(eval $(call template,issue_00623,issue_00623))
#issue_00656
$(eval $(call template,issue_00656,issue_00656))
......
regression/issue_00444/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [4:0] a;
wire [31:0] c;
always @(posedge clk)
begin
a = a + 3;
end
top uut (clk, a, c);
uut_checker c_test(.clk(clk), .A(c), .B(c));
endmodule
module uut_checker(input clk, input [31:0] A, input [31:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/issue_00457/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire b;
top uut (clk,b);
assert_X b_test(.clk(clk), .A(b));
endmodule
regression/issue_00474/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire b;
top uut (clk,b);
assert_X b_test(.clk(clk), .A(b));
endmodule
regression/issue_00474/top.v deleted 100644 → 0
module top(i_clk,b);
input i_clk;
output b;
reg f_past_gbl_clock_valid;
initial f_past_gbl_clock_valid = 0;
always @(posedge i_clk)
f_past_gbl_clock_valid <= 1'b1;
assign b = f_past_gbl_clock_valid;
endmodule
regression/issue_00481/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire b;
top uut (clk,b);
assert_X b_test(.clk(clk), .A(b));
endmodule
regression/issue_00527/syn.tcl deleted 100644 → 0
# Basic synthesis file to replicate DFFSR bug
yosys -import
set libfile osu018_stdcells_edit.lib
read_verilog -sv sd_rrmux.v
# Vanilla synth flow
hierarchy
procs
fsm
opt
techmap
opt
dfflibmap -liberty $libfile
abc -liberty $libfile
clean
write_verilog sd_rrmux_osu.gv
regression/issue_00527/testcase deleted 100644 → 0
#!/bin/bash
yosys -t syn.tcl
if grep -q DFFSR sd_rrmux_osu.gv; then
echo "FAILED -- DFFSR present in netlist"
else
echo "PASSED -- DFFSR not present"
fi
regression/issue_00567/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [3:0] i = 0;
wire b;
always @(posedge clk)
begin
i = i + 1;
end
top uut (i,b);
assert_Z b_test(.clk(clk), .A(b));
endmodule
regression/issue_00582/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [4:0] i = 0;
wire [4:0] b;
always @(posedge clk)
begin
i = i + 1;
end
main uut (b,clk);
assert_Z b_test(.clk(clk), .A(b[0]));
endmodule
regression/issue_00589/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [4:0] i = 0;
wire [4:0] b;
always @(posedge clk)
begin
i = i + 1;
end
main uut (b,clk);
assert_Z b_test(.clk(clk), .A(b[0]));
endmodule
regression/issue_00594/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [4:0] i = 0;
wire [4:0] b;
always @(posedge clk)
begin
i = i + 1;
end
main uut (b,clk);
assert_Z b_test(.clk(clk), .A(b[0]));
endmodule
regression/issue_00603/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [4:0] i = 0;
wire [4:0] b;
always @(posedge clk)
begin
i = i + 1;
end
main uut (b,clk);
assert_Z b_test(.clk(clk), .A(b[0]));
endmodule
regression/issue_00628/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [4:0] i = 0;
wire b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15,b16,b17;
always @(posedge clk)
begin
i = i + 1;
end
top uut (clk,b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15,b16,b17);
assert_Z b1_test(.clk(clk), .A(b1));
assert_Z b17_test(.clk(clk), .A(b17));
endmodule
regression/issue_00630/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [4:0] i = 0;
wire b;
always @(posedge clk)
begin
i = i + 1;
end
top uut (clk,b);
assert_Z b1_test(.clk(clk), .A(b));
endmodule
regression/issue_00635/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [4:0] i = 0;
wire b;
always @(posedge clk)
begin
i = i + 1;
end
top uut (clk,b);
assert_Z b1_test(.clk(clk), .A(b));
endmodule
regression/issue_00642/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i = 0;
reg out;
wire b;
always @(posedge clk)
begin
i = i + 1;
end
top uut (clk,i,b);
always @(posedge clk)
out <= $past(i,9);
assert_dff b1_test(.clk(clk), .test(b), .pat(out));
endmodule
regression/issue_00644/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i = 0;
reg out;
wire b;
always @(posedge clk)
begin
i = i + 1;
end
top uut (clk,i,b);
always @(posedge clk)
out <= $past(i,9);
assert_dff b1_test(.clk(clk), .test(b), .pat(out));
endmodule
regression/scripts/issue_00444.ys deleted 100644 → 0
read_verilog -formal ../top.v
hierarchy
proc_prune
proc_init
proc_mux
proc_dff
proc_clean
opt_clean
opt_merge
opt_rmdff
opt_clean
opt_expr
opt_rmdff
memory
synth -top top
write_verilog synth.v
regression/scripts/issue_00474.ys deleted 100644 → 0
read_verilog -formal ../top.v
verilog_defaults -push
verilog_defaults -pop
synth -top top
write_verilog synth.v
regression/scripts/issue_00635.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00644.ys deleted 100644 → 0
tee -o result.log read_verilog -formal ../top.v
synth -top top
write_verilog synth.v
regression_revised/Makefile
......@@ -207,8 +207,69 @@ $(eval $(call template,issue_00391,issue_00391))
#issue_00432
$(eval $(call template,issue_00432,issue_00432))
#issue_00444
$(eval $(call template,issue_00444,issue_00444))
#issue_00449
$(eval $(call template,issue_00449,issue_00449))
#issue_00457
$(eval $(call template,issue_00457,issue_00457))
#issue_00474
$(eval $(call template,issue_00474,issue_00474))
#issue_00481
$(eval $(call template,issue_00481,issue_00481))
#issue_00502
$(eval $(call template,issue_00502,issue_00502))
#issue_00524
$(eval $(call template,issue_00524,issue_00524))
#issue_00527
$(eval $(call template,issue_00527,issue_00527))
#issue_00567
$(eval $(call template,issue_00567,issue_00567))
#issue_00582
$(eval $(call template,issue_00582,issue_00582_fail))
#issue_00589
$(eval $(call template,issue_00589,issue_00589))
#issue_00594
$(eval $(call template,issue_00594,issue_00594_fail))
#issue_00603
$(eval $(call template,issue_00603,issue_00603_fail))
#issue_00628
$(eval $(call template,issue_00628,issue_00628))
#issue_00630
$(eval $(call template,issue_00630,issue_00630))
#issue_00635
$(eval $(call template,issue_00635,issue_00635_fail))
#issue_00639
$(eval $(call template,issue_00639,issue_00639_fail))
#issue_00642
$(eval $(call template,issue_00642,issue_00642))
#issue_00644
$(eval $(call template,issue_00644,issue_00644))
#Still open bugs (should be failed):
#issue_00329
$(eval $(call template,issue_00329,issue_00329))
#issue_00623
$(eval $(call template,issue_00623,issue_00623))
.PHONY: all clean
regression_revised/issue_00444/issue_00444.ys 0 → 100644
read_verilog -formal ../top.v
prep -top top
regression_revised/issue_00481/issue_00481.ys 0 → 100644
read_verilog ../top.v
synth_ice40 -blif tlt.blif
regression/scripts/issue_00567.ys → regression_revised/issue_00567/issue_00567.ys
......@@ -2,5 +2,3 @@ read_verilog ../top.v
synth_ice40 -nocarry
opt_clean
write_blif -attr -cname -param lut.eblif
write_verilog synth.v
regression_revised/issue_00582/issue_00582_fail.pat 0 → 100644
ERROR: Failed to detect width for identifier \\valid!
regression/scripts/issue_00582.ys → regression_revised/issue_00582/issue_00582_fail.ys
read_verilog ../top.v
synth_ice40 -top main -blif stencil.blif
write_verilog synth.v
regression/scripts/issue_00589.ys → regression_revised/issue_00589/issue_00589.ys
......@@ -12,7 +12,4 @@ share -aggressive -force
opt
fsm
opt -fast
write_ilang dump.ilang
synth -top main
write_verilog synth.v
select -assert-count 1 t:$memrd
regression/scripts/issue_00481.ys → regression_revised/issue_00594/issue_00594_fail.ys
read_verilog ../top.v
synth_ice40 -blif tlt.blif -top top
write_verilog synth.v
regression/scripts/issue_00628.ys → regression_revised/issue_00628/issue_00628.ys
......@@ -11,7 +11,6 @@ abc -script +strash
#retime
#strash
clean
write_blif
synth_ice40 -top top
write_verilog synth.v
#write_blif
select -assert-count 16 t:SB_LUT4
regression/scripts/issue_00630.ys → regression_revised/issue_00630/issue_00630.ys
read_verilog ../top.v
hierarchy
synth_ice40 -blif demo.blif
write_verilog synth.v
tee -o result.out synth_ice40 -blif demo.blif
regression_revised/issue_00630/issue_00630_n.pat 0 → 100644
Warning: wire '$func$\func$demo.v:8$2$\arg' is assigned in a block at demo.v:4.
regression_revised/issue_00639/issue_00639_fail.pat 0 → 100644
ERROR: Found 3 unproven \$equiv cells in 'equiv_status -assert'.
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