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lvzhengyang
yosys-tests
Commits
0dd66c74
Commit
0dd66c74
authored
May 03, 2019
by
Eddie Hung
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Fix remaining tests
parent
d8fdc57e
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architecture/synth_xilinx_srl/generate.py
+2
-2
architecture/synth_xilinx_srl/test18.ys
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architecture/synth_xilinx_srl/test19.ys
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architecture/synth_xilinx_srl/generate.py
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0dd66c74
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@@ -247,7 +247,7 @@ generate
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@@ -247,7 +247,7 @@ generate
end
end
end
end
end
end
assign
z
= int[depth-1];
assign
q
= int[depth-1];
endgenerate
endgenerate
endmodule'''
.
format
(
i
))
endmodule'''
.
format
(
i
))
...
@@ -272,6 +272,6 @@ generate
...
@@ -272,6 +272,6 @@ generate
end
end
end
end
end
end
assign
z
= int[l];
assign
q
= int[l];
endgenerate
endgenerate
endmodule'''
.
format
(
i
))
endmodule'''
.
format
(
i
))
architecture/synth_xilinx_srl/test18.ys
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0dd66c74
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architecture/synth_xilinx_srl/test19.ys
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