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yosys-tests
Commit 0bb6dfd2 by SergeyDegtyar
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Add new test group 'yosys'

parent 0c5b0c30
Showing with 1748 additions and 1 deletions
Makefile
SUBDIRS := architecture backends bigsim equiv frontends misc regression simple SUBDIRS := architecture backends bigsim equiv frontends misc regression simple yosys
ifeq ($(VERIFIC),1) ifeq ($(VERIFIC),1)
export VERIFIC=1 export VERIFIC=1
......
yosys/.gitignore 0 → 100644
*/work_*/
/.stamp
yosys/Makefile 0 → 100644
all: work
touch .stamp
clean::
rm -f .stamp
define template
$(foreach design,$(1),
$(foreach script,$(2),
work:: $(design)/work_$(script)/.stamp
$(design)/work_$(script)/.stamp:
./run.sh $(design) $(script)
clean::
rm -rf $(design)/work_$(script)
))
endef
#yosys
$(eval $(call template,yosys,yosys))
#yosys_help
$(eval $(call template,yosys_help,yosys))
#yosys_no_banner
$(eval $(call template,yosys_no_banner,yosys))
#yosys_no_footer
$(eval $(call template,yosys_no_footer,yosys))
#yosys_quiet
$(eval $(call template,yosys_quiet,yosys))
#yosys_headers
$(eval $(call template,yosys_headers,yosys))
#yosys_time
$(eval $(call template,yosys_time,yosys))
#yosys_detailed_timing
$(eval $(call template,yosys_detailed_timing,yosys))
#yosys_log_file
$(eval $(call template,yosys_log_file,yosys))
#yosys_log_file_lb_mode
$(eval $(call template,yosys_log_file_lb_mode,yosys))
#yosys_write_des_to_file
$(eval $(call template,yosys_write_des_to_file,yosys))
#yosys_backends
$(eval $(call template,yosys_backends,yosys))
#yosys_frontends
$(eval $(call template,yosys_frontends,yosys))
#yosys_command_list
$(eval $(call template,yosys_command_list,yosys))
#yosys_help_for_command
$(eval $(call template,yosys_help_for_command,yosys))
#yosys_script
$(eval $(call template,yosys_script,yosys))
#yosys_tcl_script
$(eval $(call template,yosys_tcl_script,yosys))
#yosys_exec_command
$(eval $(call template,yosys_exec_command,yosys))
#yosys_enable_tracing
$(eval $(call template,yosys_enable_tracing,yosys))
#yosys_randomize_alloc_point_addr
$(eval $(call template,yosys_randomize_alloc_point_addr,yosys))
#yosys_abort
$(eval $(call template,yosys_abort,yosys))
#yosys_macro
$(eval $(call template,yosys_macro,yosys))
#yosys_header
$(eval $(call template,yosys_header,yosys))
#yosys_regexp
$(eval $(call template,yosys_regexp,yosys))
#yosys_regexp_w
$(eval $(call template,yosys_regexp_w,yosys))
#yosys_regexp_e
$(eval $(call template,yosys_regexp_e,yosys))
#yosys_dependencies
$(eval $(call template,yosys_dependencies,yosys))
#yosys_globally_en_log_mes
$(eval $(call template,yosys_globally_en_log_mes,yosys))
#yosys_version
$(eval $(call template,yosys_version,yosys))
#yosys_synth
$(eval $(call template,yosys_synth,yosys))
.PHONY: all clean
yosys/run.sh 0 → 100755
#!/bin/bash
set -x
test -d $1
test -f scripts/$2.ys
rm -rf $1/work_$2
mkdir $1/work_$2
cd $1/work_$2
touch .start
expected_string=""
expected="1"
if [ "$1" = "yosys" ]; then
expected_string="yosys -- Yosys Open SYnthesis Suite"
elif [ "$1" = "yosys_help" ]; then
expected_string="print the help message for the specified command"
elif [ "$1" = "yosys_no_banner" ]; then
expected_string="yosys -- Yosys Open SYnthesis Suite"
expected="0"
elif [ "$1" = "yosys_no_footer" ]; then
expected_string="End of script. Logfile hash:"
expected="0"
elif [ "$1" = "yosys_quiet" ]; then
expected_string="yosys"
expected="0"
elif [ "$1" = "yosys_headers" ]; then
expected_string="yosys"
expected="0"
elif [ "$1" = "yosys_time" ]; then
expected_string="\[00000.000000\]"
elif [ "$1" = "yosys_detailed_timing" ]; then
expected_string=" calls"
elif [ "$1" = "yosys_log_file" ]; then
expected_string="yosys -- Yosys Open SYnthesis Suite"
elif [ "$1" = "yosys_log_file_lb_mode" ]; then
expected_string="yosys -- Yosys Open SYnthesis Suite"
elif [ "$1" = "yosys_write_des_to_file" ]; then
expected_string="Generated by Yosys"
elif [ "$1" = "yosys_backends" ]; then
expected_string="Generated by Yosys"
elif [ "$1" = "yosys_frontends" ]; then
expected_string="Parsing \`../top.v' using frontend \`verilog'"
elif [ "$1" = "yosys_command_list" ]; then
expected_string="abc"
elif [ "$1" = "yosys_help_for_command" ]; then
expected_string="abc \[options\] \[selection\]"
elif [ "$1" = "yosys_script" ]; then
expected_string="Executing script file \`../run_script.ys'"
elif [ "$1" = "yosys_tcl_script" ]; then
expected_string="Run tcl script!"
elif [ "$1" = "yosys_exec_command" ]; then
expected_string="abc"
elif [ "$1" = "yosys_enable_tracing" ]; then
expected_string="abc"
elif [ "$1" = "yosys_randomize_alloc_point_addr" ]; then
expected_string="abc"
elif [ "$1" = "yosys_abort" ]; then
expected_string="abc"
elif [ "$1" = "yosys_macro" ]; then
expected_string="abc"
elif [ "$1" = "yosys_header" ]; then
expected_string=" Parsing \`../top.v' using frontend \`verilog'"
elif [ "$1" = "yosys_regexp" ]; then
expected_string="abc"
elif [ "$1" = "yosys_regexp_w" ]; then
expected_string="abc"
elif [ "$1" = "yosys_regexp_e" ]; then
expected_string="abc"
elif [ "$1" = "yosys_dependencies" ]; then
expected_string="abc"
elif [ "$1" = "yosys_globally_en_log_mes" ]; then
expected_string="abc"
elif [ "$1" = "yosys_version" ]; then
expected_string="Yosys "
elif [ "$1" = "yosys_synth" ]; then
expected_string="Running command \`synth'"
fi
../run_yosys.sh
if [ "$1"! = "yosys_abort" ]; then
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
fi
if grep "$expected_string" yosys.log; then
if [ $expected = "1" ]; then
echo PASS > ${1}_${2}.status
else
echo FAIL > ${1}_${2}.status
fi
else
if [ $expected = "1" ]; then
echo FAIL > ${1}_${2}.status
else
echo PASS > ${1}_${2}.status
fi
fi
touch .stamp
yosys/yosys/run_yosys.sh 0 → 100755
#!/bin/bash
yosys ../run_script.ys >> yosys.log
yosys/yosys/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_abort/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -A ../run_script.ys >> yosys.log
yosys/yosys_abort/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_backends/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -b blif ../run_script.ys >> yosys.log
yosys/yosys_backends/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_command_list/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -H >> yosys.log
yosys/yosys_command_list/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_dependencies/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -E tt.txt ../run_script.ys >> yosys.log
yosys/yosys_dependencies/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_detailed_timing/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -d ../run_script.ys >> yosys.log
yosys/yosys_detailed_timing/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_enable_tracing/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -X ../run_script.ys >> yosys.log
yosys/yosys_enable_tracing/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_exec_command/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -p help >> yosys.log
yosys/yosys_exec_command/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_frontends/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -f verilog ../top.v >> yosys.log
yosys/yosys_frontends/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_globally_en_log_mes/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -g ../run_script.ys >> yosys.log
yosys/yosys_globally_en_log_mes/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_header/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -P TOP:top.v ../top.v >> yosys.log
yosys/yosys_header/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_headers/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -v 3 ../run_script.ys >> yosys.log
yosys/yosys_headers/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_help/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -h >> yosys.log
yosys/yosys_help/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_help_for_command/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -h abc >> yosys.log
yosys/yosys_help_for_command/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_log_file/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -l yosys.log ../run_script.ys
yosys/yosys_log_file/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_log_file_lb_mode/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -L yosys.log ../run_script.ys
yosys/yosys_log_file_lb_mode/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_macro/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -D YOSYS ../run_script.ys >> yosys.log
yosys/yosys_macro/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_no_banner/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -Q ../run_script.ys >> yosys.log
yosys/yosys_no_banner/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_no_footer/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -T ../run_script.ys >> yosys.log
yosys/yosys_no_footer/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_quiet/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -q ../run_script.ys >> yosys.log
yosys/yosys_quiet/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_randomize_alloc_point_addr/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -M ../run_script.ys >> yosys.log
yosys/yosys_randomize_alloc_point_addr/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_regexp/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -W Parsing ../run_script.ys >> yosys.log
yosys/yosys_regexp/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_regexp_e/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -e abc ../run_script.ys >> yosys.log
yosys/yosys_regexp_e/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_regexp_w/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -w abc ../run_script.ys >> yosys.log
yosys/yosys_regexp_w/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_script/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -s ../run_script.ys >> yosys.log
yosys/yosys_script/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_synth/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -S ../run_script.ys >> yosys.log
yosys/yosys_synth/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_tcl_script/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -c ../run_script.tcl >> yosys.log
yosys/yosys_tcl_script/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_time/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -t ../run_script.ys >> yosys.log
yosys/yosys_time/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_version/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -V ../run_script.ys >> yosys.log
yosys/yosys_version/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys/yosys_write_des_to_file/run_yosys.sh 0 → 100755
#!/bin/bash
yosys -o yosys.blif ../run_script.ys
cp yosys.blif yosys.log
yosys/yosys_write_des_to_file/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
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