Commit 074b684f by SergeyDegtyar

remove string checking for some tests.

parent c8f6ef8f
...@@ -60,6 +60,29 @@ if [ "$1" = "issue_00089" ] ||\ ...@@ -60,6 +60,29 @@ if [ "$1" = "issue_00089" ] ||\
fi fi
fi fi
# cases without any additional checks (only checks in .ys script)
elif [ "$1" = "issue_01364" ] ||\
[ "$1" = "issue_01372" ] ||\
[ "$1" = "issue_00623" ] ||\
[ "$1" = "issue_00656" ] ||\
[ "$1" = "issue_01014" ] ||\
[ "$1" = "issue_01193" ] ||\
[ "$1" = "issue_01206" ] ||\
[ "$1" = "issue_01216" ] ||\
[ "$1" = "issue_01225" ] ||\
[ "$1" = "issue_01259" ] ||\
[ "$1" = "issue_01360" ]; then
yosys -ql yosys.log ../../scripts/$2.ys;
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
else
echo PASS > ${1}_${2}.status
fi
# cases where some object names are/aren't expected in output file (tee -o result.log in the test script) # cases where some object names are/aren't expected in output file (tee -o result.log in the test script)
elif [ "$1" = "issue_00502" ] ||\ elif [ "$1" = "issue_00502" ] ||\
[ "$1" = "issue_00524" ] ||\ [ "$1" = "issue_00524" ] ||\
...@@ -129,19 +152,10 @@ elif [ "$1" = "issue_00502" ] ||\ ...@@ -129,19 +152,10 @@ elif [ "$1" = "issue_00502" ] ||\
[ "$1" = "issue_01243" ] ||\ [ "$1" = "issue_01243" ] ||\
[ "$1" = "issue_01273" ] ||\ [ "$1" = "issue_01273" ] ||\
[ "$1" = "issue_01329" ] ||\ [ "$1" = "issue_01329" ] ||\
[ "$1" = "issue_01364" ] ||\
[ "$1" = "issue_01372" ] ||\
[ "$1" = "issue_00329" ] ||\ [ "$1" = "issue_00329" ] ||\
[ "$1" = "issue_00623" ] ||\
[ "$1" = "issue_01014" ] ||\
[ "$1" = "issue_01126" ] ||\ [ "$1" = "issue_01126" ] ||\
[ "$1" = "issue_01161" ] ||\ [ "$1" = "issue_01161" ] ||\
[ "$1" = "issue_01193" ] ||\
[ "$1" = "issue_01206" ] ||\
[ "$1" = "issue_01216" ] ||\
[ "$1" = "issue_01217" ] ||\ [ "$1" = "issue_01217" ] ||\
[ "$1" = "issue_01225" ] ||\
[ "$1" = "issue_01259" ] ||\
[ "$1" = "issue_01291" ]; then [ "$1" = "issue_01291" ]; then
expected_string="" expected_string=""
...@@ -271,8 +285,7 @@ elif [ "$1" = "issue_00502" ] ||\ ...@@ -271,8 +285,7 @@ elif [ "$1" = "issue_00502" ] ||\
expected_string="Executing FLATTEN pass (flatten design)." expected_string="Executing FLATTEN pass (flatten design)."
elif [ "$1" = "issue_01223" ]; then elif [ "$1" = "issue_01223" ]; then
expected_string=" Executing CHECK pass (checking for obvious problems)." expected_string=" Executing CHECK pass (checking for obvious problems)."
elif [ "$1" = "issue_01231" ] ||\ elif [ "$1" = "issue_01231" ]; then
[ "$1" = "issue_01364" ]; then
expected_string="Successfully finished Verilog frontend." expected_string="Successfully finished Verilog frontend."
elif [ "$1" = "issue_01243" ]; then elif [ "$1" = "issue_01243" ]; then
expected_string="assign y = reg_assign;" expected_string="assign y = reg_assign;"
...@@ -280,40 +293,19 @@ elif [ "$1" = "issue_00502" ] ||\ ...@@ -280,40 +293,19 @@ elif [ "$1" = "issue_00502" ] ||\
expected_string="\$_MUX8_ 9" expected_string="\$_MUX8_ 9"
elif [ "$1" = "issue_01329" ]; then elif [ "$1" = "issue_01329" ]; then
expected_string="\$mux 1" expected_string="\$mux 1"
elif [ "$1" = "issue_01372" ]; then
expected_string="input \\[1:0\\] s"
elif [ "$1" = "issue_00329" ]; then elif [ "$1" = "issue_00329" ]; then
expected_string="wire \\[-1" expected_string="wire \\[-1"
elif [ "$1" = "issue_00623" ]; then expected="0"
expected_string="IOBUF _4_"
elif [ "$1" = "issue_00656" ]; then
expected_string="Successfully finished Verilog frontend."
elif [ "$1" = "issue_01014" ]; then
expected_string="Successfully finished Verilog frontend."
elif [ "$1" = "issue_01126" ]; then elif [ "$1" = "issue_01126" ]; then
expected_string="assign d = c\\[5:0\\]" expected_string="assign d = c\\[5:0\\]"
elif [ "$1" = "issue_01161" ]; then elif [ "$1" = "issue_01161" ]; then
expected_string="assign z0 = b" expected_string="assign z0 = b"
elif [ "$1" = "issue_01193" ]; then
expected_string="cell \$dlatch"
expected="0"
elif [ "$1" = "issue_01206" ]; then
expected_string="Executing PROC_INIT pass"
elif [ "$1" = "issue_01216" ]; then
expected_string="ERROR: Assert"
expected="0"
elif [ "$1" = "issue_01217" ]; then elif [ "$1" = "issue_01217" ]; then
expected_string="is implicitly declared." expected_string="is implicitly declared."
expected="0" expected="0"
elif [ "$1" = "issue_01225" ]; then
expected_string="cell \OBUFT"
elif [ "$1" = "issue_01259" ]; then
expected_string="Executing SMT2 backend"
elif [ "$1" = "issue_01291" ]; then elif [ "$1" = "issue_01291" ]; then
expected_string="connect \\\out 1'x" expected_string="connect \\\out 1'x"
expected="0" expected="0"
elif [ "$1" = "issue_01360" ]; then
expected_string="Executing BLIF backend"
fi fi
if [ "$1" = "issue_01118" ]; then if [ "$1" = "issue_01118" ]; then
......
...@@ -2,4 +2,4 @@ read_verilog ../top.v ...@@ -2,4 +2,4 @@ read_verilog ../top.v
tribuf -logic tribuf -logic
synth -top bidirtest synth -top bidirtest
iopadmap -bits -inpad IBUF O:PAD -outpad OBUF I:PAD -tinoutpad IOBUF ENA:O:I:PAD bidirtest iopadmap -bits -inpad IBUF O:PAD -outpad OBUF I:PAD -tinoutpad IOBUF ENA:O:I:PAD bidirtest
write_verilog -noattr result.log select -assert-count 0 t:IOBUF
tee -o result.log read_verilog ../top.v read_verilog ../top.v
synth synth
write_verilog synth.v
...@@ -5,5 +5,6 @@ proc ...@@ -5,5 +5,6 @@ proc
write_verilog result_no_opt.log write_verilog result_no_opt.log
equiv_opt -assert opt_clean
opt_clean opt_clean
write_verilog result.log write_verilog result.log
read_verilog -sv ../top.v read_verilog -sv ../top.v
proc proc
select -assert-count 0 t:$dlatch
tee -o result.log dump
tee -o result.log read_verilog ../top.v read_verilog ../top.v
synth_xilinx synth_xilinx
tee -o result.log dump select -assert-count 1 t:BUFT
tee -o result.log read_verilog ../top.v tee -o result.log read_verilog ../top.v
proc
equiv_opt -assert prep
prep -top frozen prep -top frozen
tee -o result.log dump tee -o result.log dump
read_verilog -sv ../top.v; read_verilog -sv ../top.v
tee -o result.log synth_ice40 -blif out.blif synth_ice40 -blif out.blif
tee -o result.log read_verilog ../top.v read_verilog ../top.v
read -define BROKEN_CODE read -define BROKEN_CODE
read -formal ../top.v read -formal ../top.v
prep -top mcvesix prep -top mcvesix
write_verilog result.log tee -o result.log equiv_opt -assert prep # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mcvesix # Constrain all select calls below inside the top module
select -assert-count 2 w:k s:32
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