Few more regression fixes

architecture/synth_xilinx/synth_xilinx_nodram.ys

@@ -16,8 +16,8 @@ design -load postopt
 cd top
 select -assert-count 2 t:BUFG
 select -assert-count 6 t:FDRE
-select -assert-count 6 t:RAM64X1D
-select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
+select -assert-count 2 t:RAM64M
+select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D
 
 design -load read
 hierarchy -top top
@@ -35,10 +35,11 @@ cd top
 
 select -assert-count 2 t:BUFG
 select -assert-count 390 t:FDRE
-select -assert-count 90 t:LUT2
-select -assert-count 10 t:LUT4
+select -assert-count 2 t:LUT2
+select -assert-count 385 t:LUT3
+select -assert-count 9 t:LUT4
 select -assert-count 1 t:LUT5
-select -assert-count 158 t:LUT6
-select -assert-count 37 t:MUXF7
-select -assert-count 1 t:MUXF8
-select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
+select -assert-count 223 t:LUT6
+select -assert-count 36 t:MUXF7
+select -assert-count 3 t:MUXF8
+select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D

backends/write_intersynth/write_intersynth__latches.pat

-node $auto$proc_dlatch.cc:417:proc_dlatch$4 $dlatch Q q D $procmux$2_Y EN $auto$rtlil.cc:1844:Not$14 WIDTH 0x1 EN_POLARITY 0x1
-node $auto$proc_dlatch.cc:417:proc_dlatch$5 $not Y $auto$rtlil.cc:1844:Not$14 A $auto$rtlil.cc:1848:ReduceOr$13 Y_WIDTH 0x1 A_WIDTH 0x1 A_SIGNED 0x0
+$dlatch Q q D $procmux$2_Y EN
\ No newline at end of file

backends/write_table/write_table__latches.pat

-op	$auto$proc_dlatch.cc:417:proc_dlatch$4	$dlatch	D	in	$procmux$2_Y
-top	$auto$proc_dlatch.cc:417:proc_dlatch$4	$dlatch	EN	in	$auto$rtlil.cc:1844:Not$14
-top	$auto$proc_dlatch.cc:417:proc_dlatch$4	$dlatch	Q	out	\q
\ No newline at end of file
+$dlatch	D	in	$procmux$2_Y
\ No newline at end of file

simple/submod/submod_error_fail.pat

-ERROR: More than one module selected: \\top \\fsm2
+ERROR: More than one module selected: \\top \\fsm
\ No newline at end of file