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Commit 050cc693 by SergeyDegtyar
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Fix all review comments form Clifford Wolf

parent 957b69f0
Showing with 338 additions and 417 deletions
simple/Makefile
...@@ -20,7 +20,7 @@ endef ...@@ -20,7 +20,7 @@ endef
$(eval $(call template,alu,gates luts)) $(eval $(call template,alu,gates luts))
# DFF with constant drivers # DFF with constant drivers
$(eval $(call template,dff, dff)) $(eval $(call template,dff_d0, dff))
$(eval $(call template,dffr, dff)) $(eval $(call template,dffr, dff))
$(eval $(call template,dffc, dff)) $(eval $(call template,dffc, dff))
$(eval $(call template,dffcp, dff)) $(eval $(call template,dffcp, dff))
......
simple/common.v 0 → 100644
module assert_dff(input clk, input test, input pat);
always @(posedge clk)
begin
if (test != pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time);
$stop;
end
end
endmodule
module assert_tri(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
module assert_Z(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A === 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
simple/dff/testbench.v → simple/dff_d0/testbench.v
...@@ -15,33 +15,20 @@ module testbench; ...@@ -15,33 +15,20 @@ module testbench;
end end
reg dinA; reg dinA = 0;
wire dinB; wire doutB;
top uut ( top uut (
.clk (clk ), .clk (clk ),
.a (dinA ), .a (dinA ),
.b (dinB ) .b (doutB )
); );
initial begin always @(posedge clk) begin
dinA <= 0; #3;
dinA <= !dinA;
repeat (20000) #3 dinA = !dinA;
end
assert ff_test(.clk(clk), .test(dinB));
endmodule
module assert(input clk, input test);
always @(posedge clk)
begin
if (test == 1)
begin
$display("ASSERTION FAILED in %m:",$time);
//$finish;
end
end end
assert_dff ff_test(.clk(clk), .test(doutB), .pat(1'b0));
endmodule endmodule
simple/dff/top.v → simple/dff_d0/top.v
...@@ -16,7 +16,11 @@ output b ...@@ -16,7 +16,11 @@ output b
dff u_dff ( dff u_dff (
.clk (clk ), .clk (clk ),
`ifndef BUG
.d (1'b0 ), .d (1'b0 ),
`else
.d (a ),
`endif
.q (b ) .q (b )
); );
......
simple/dffc/testbench.v
...@@ -14,46 +14,32 @@ module testbench; ...@@ -14,46 +14,32 @@ module testbench;
$display("OKAY"); $display("OKAY");
end end
function [31:0] xorshift32;
input [31:0] arg;
begin
xorshift32 = arg;
// Xorshift32 RNG, doi:10.18637/jss.v008.i14
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
reg [31:0] rng = 123456789;
always @(posedge clk) rng <= xorshift32(rng);
wire dinA = xorshift32(rng * 5);
wire dinC = xorshift32(rng * 7);
reg dinA; wire doutB;
reg dinC;
wire dinB;
top uut ( top uut (
.clk (clk ), .clk (clk ),
.a (dinA ), .a (dinA ),
.c (dinC), .c (dinC),
.b (dinB ) .b (doutB )
); );
initial begin assert_dff ff_test(.clk(clk), .test(doutB), .pat(1'b1));
dinC <= 1;
#5
dinC <= 0;
#10
dinC <= 1;
#10
dinC <= 0;
end
initial begin
dinA <= 0;
repeat (20000) #3 dinA = !dinA;
end
assert ff_test(.clk(clk), .test(dinB));
endmodule endmodule
module assert(input clk, input test);
always @(posedge clk)
begin
if (test == 0)
begin
$display("ASSERTION FAILED in %m:",$time);
//$finish;
end
end
endmodule
simple/dffc/top.v
...@@ -20,7 +20,11 @@ output b ...@@ -20,7 +20,11 @@ output b
dffcp u_dffcp ( dffcp u_dffcp (
.clk (clk ), .clk (clk ),
.clr (c ), .clr (c ),
`ifndef BUG
.pre (1'b1), .pre (1'b1),
`else
.pre (1'b0),
`endif
.d (a ), .d (a ),
.q (b ) .q (b )
); );
......
simple/dffcp/testbench.v
...@@ -15,33 +15,20 @@ module testbench; ...@@ -15,33 +15,20 @@ module testbench;
end end
reg dinA; reg dinA = 0;
wire dinB; wire doutB;
top uut ( top uut (
.clk (clk ), .clk (clk ),
.a (dinA ), .a (dinA ),
.b (dinB ) .b (doutB )
); );
initial begin always @(posedge clk) begin
dinA <= 0; #3;
dinA <= !dinA;
repeat (20000) #3 dinA = !dinA; end
end
assert ff_test(.clk(clk), .test(dinB)); assert_dff ff_test(.clk(clk), .test(doutB), .pat(1'b1));
endmodule endmodule
module assert(input clk, input test);
always @(posedge clk)
begin
if (test == 0)
begin
$display("ASSERTION FAILED in %m:",$time);
//$finish;
end
end
endmodule
simple/dffcp/top.v
...@@ -17,8 +17,13 @@ output b ...@@ -17,8 +17,13 @@ output b
dffcp u_dffcp ( dffcp u_dffcp (
.clk (clk ), .clk (clk ),
`ifndef BUG
.clr (1'b0), .clr (1'b0),
.pre (1'b1), .pre (1'b1),
`else
.clr (1'b1),
.pre (1'b0),
`endif
.d (a ), .d (a ),
.q (b ) .q (b )
); );
......
simple/dffr/testbench.v
...@@ -15,33 +15,20 @@ module testbench; ...@@ -15,33 +15,20 @@ module testbench;
end end
reg dinA; reg dinA = 0;
wire dinB; wire doutB;
top uut ( top uut (
.clk (clk ), .clk (clk ),
.a (dinA ), .a (dinA ),
.b (dinB ) .b (doutB )
); );
initial begin always @(posedge clk) begin
dinA <= 0; #3;
dinA <= !dinA;
repeat (20000) #3 dinA = !dinA;
end
assert ff_test(.clk(clk), .test(dinB));
endmodule
module assert(input clk, input test);
always @(posedge clk)
begin
if (test == 1)
begin
$display("ASSERTION FAILED in %m:",$time);
//$finish;
end
end end
assert_dff ff_test(.clk(clk), .test(doutB), .pat(1'b0));
endmodule endmodule
simple/dffr/top.v
...@@ -16,7 +16,11 @@ output b ...@@ -16,7 +16,11 @@ output b
dffr u_dffr ( dffr u_dffr (
.clk (clk), .clk (clk),
`ifndef BUG
.rst (1'b1), .rst (1'b1),
`else
.rst (1'b0),
`endif
.d (a ), .d (a ),
.q (b ) .q (b )
); );
......
simple/dffsr/testbench.v
...@@ -15,33 +15,20 @@ module testbench; ...@@ -15,33 +15,20 @@ module testbench;
end end
reg dinA; reg dinA = 0;
wire dinB; wire doutB;
top uut ( top uut (
.clk (clk ), .clk (clk ),
.a (dinA ), .a (dinA ),
.b (dinB ) .b (doutB )
); );
initial begin always @(posedge clk) begin
dinA <= 0; #3;
dinA <= !dinA;
repeat (20000) #3 dinA = !dinA;
end
assert ff_test(.clk(clk), .test(dinB));
endmodule
module assert(input clk, input test);
always @(posedge clk)
begin
if (test == 0)
begin
$display("ASSERTION FAILED in %m:",$time);
//$finish;
end
end end
assert_dff ff_test(.clk(clk), .test(doutB), .pat(1'b1));
endmodule endmodule
simple/dffsr/top.v
...@@ -17,8 +17,13 @@ output b ...@@ -17,8 +17,13 @@ output b
dffsr u_dffsr ( dffsr u_dffsr (
.clk (clk ), .clk (clk ),
`ifndef BUG
.clr (1'b1), .clr (1'b1),
.pre (1'b1), .pre (1'b1),
`else
.clr (1'b0),
.pre (1'b0),
`endif
.d (a ), .d (a ),
.q (b ) .q (b )
); );
......
simple/fsm/testbench.v
...@@ -14,9 +14,22 @@ module testbench; ...@@ -14,9 +14,22 @@ module testbench;
$display("OKAY"); $display("OKAY");
end end
function [31:0] xorshift32;
reg a; input [31:0] arg;
reg b; begin
xorshift32 = arg;
// Xorshift32 RNG, doi:10.18637/jss.v008.i14
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
reg [31:0] rng = 123456789;
always @(posedge clk) rng <= xorshift32(rng);
wire a = xorshift32(rng * 5);
wire b = xorshift32(rng * 7);
reg rst; reg rst;
wire g0; wire g0;
wire g1; wire g1;
...@@ -36,30 +49,7 @@ module testbench; ...@@ -36,30 +49,7 @@ module testbench;
rst <= 0; rst <= 0;
end end
initial begin assert_Z g0_test(.clk(clk), .A(g0));
a <= 0; assert_Z g1_test(.clk(clk), .A(g1));
repeat (20000) #3 a = !a;
end
initial begin
b <= 0;
repeat (20000) #4 b = !b;
end
assert g0_test(.clk(clk), .A(g0));
assert g1_test(.clk(clk), .A(g1));
endmodule endmodule
module assert(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
begin
$display("ASSERTION FAILED in %m:",$time," ",A);
//$finish;
end
end
endmodule
simple/fsm/top.v
...@@ -27,7 +27,11 @@ ...@@ -27,7 +27,11 @@
case(state) case(state)
IDLE : if (req_0 == 1'b1) begin IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0; state <= #1 GNT0;
`ifndef BUG
gnt_0 <= 1; gnt_0 <= 1;
`else
gnt_0 <= 1'bZ;
`endif
end else if (req_1 == 1'b1) begin end else if (req_1 == 1'b1) begin
gnt_1 <= 1; gnt_1 <= 1;
state <= #1 GNT0; state <= #1 GNT0;
......
simple/fsm_opt/testbench.v
...@@ -14,9 +14,22 @@ module testbench; ...@@ -14,9 +14,22 @@ module testbench;
$display("OKAY"); $display("OKAY");
end end
function [31:0] xorshift32;
reg a; input [31:0] arg;
reg b; begin
xorshift32 = arg;
// Xorshift32 RNG, doi:10.18637/jss.v008.i14
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
reg [31:0] rng = 123456789;
always @(posedge clk) rng <= xorshift32(rng);
wire a = xorshift32(rng * 5);
wire b = xorshift32(rng * 7);
reg rst; reg rst;
wire g0; wire g0;
wire g1; wire g1;
...@@ -36,30 +49,7 @@ module testbench; ...@@ -36,30 +49,7 @@ module testbench;
rst <= 0; rst <= 0;
end end
initial begin assert_Z g0_test(.clk(clk), .A(g0));
a <= 0; assert_Z g1_test(.clk(clk), .A(g1));
repeat (20000) #3 a = !a;
end
initial begin
b <= 0;
repeat (20000) #4 b = !b;
end
assert g0_test(.clk(clk), .A(g0));
assert g1_test(.clk(clk), .A(g1));
endmodule endmodule
module assert(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
begin
$display("ASSERTION FAILED in %m:",$time," ",A);
//$finish;
end
end
endmodule
simple/fsm_opt/top.v
...@@ -27,7 +27,11 @@ ...@@ -27,7 +27,11 @@
case(state) case(state)
IDLE : if (req[0] == 1'b1) begin IDLE : if (req[0] == 1'b1) begin
state <= #1 GNT0; state <= #1 GNT0;
`ifndef BUG
gnt[0] <= 1; gnt[0] <= 1;
`else
gnt[0] <= 1'bZ;
`endif
end else if (req[1] == 1'b1) begin end else if (req[1] == 1'b1) begin
gnt[1] <= 1; gnt[1] <= 1;
state <= #1 GNT0; state <= #1 GNT0;
......
simple/fsm_unreach/testbench.v
...@@ -23,7 +23,7 @@ module testbench; ...@@ -23,7 +23,7 @@ module testbench;
wire [4:0] y; wire [4:0] y;
wire [4:0] z; wire [4:0] z;
top uut ( top uut_fsm (
.clk (clk), .clk (clk),
.rst (rst), .rst (rst),
.a (a), .a (a),
...@@ -35,44 +35,53 @@ module testbench; ...@@ -35,44 +35,53 @@ module testbench;
); );
initial begin initial begin
rst <= 0; rst <= 0;
#5 #5
rst <= 1; rst <= 1;
#5 #5
rst <= 0; rst <= 0;
#5 #5
@(posedge clk);
a <= 4'b1111; a <= 4'b1111;
b <= 4'b1010; b <= 4'b1010;
c <= 4'b1011; c <= 4'b1011;
#50
repeat (10) @(posedge clk);
a <= 4'b1000; a <= 4'b1000;
b <= 4'b1100; b <= 4'b1100;
c <= 4'b1010; c <= 4'b1010;
#50
repeat (10) @(posedge clk);
a <= 4'b1100; a <= 4'b1100;
b <= 4'b0100; b <= 4'b0100;
c <= 4'b1011; c <= 4'b1011;
#50
repeat (10) @(posedge clk);
a <= 4'b1101; a <= 4'b1101;
b <= 4'b1110; b <= 4'b1110;
c <= 4'b0000; c <= 4'b0000;
end end
assert x_test(.clk(clk), .A(x)); uut_fsm_checker x_test(.clk(clk), .A(x));
assert y_test(.clk(clk), .A(y)); uut_fsm_checker y_test(.clk(clk), .A(y));
assert z_test(.clk(clk), .A(z)); uut_fsm_checker z_test(.clk(clk), .A(z));
endmodule endmodule
module assert(input clk, input [4:0] A); module uut_fsm_checker(input clk, input [4:0] A);
always @(posedge clk) always @(posedge clk)
begin begin
//#1; //#1;
if (A == 4'b0000) if (A == 4'b0000)
begin begin
$display("ASSERTION FAILED in %m:",$time," ",A); $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
//$finish; $stop;
end end
end end
endmodule endmodule
simple/fsm_unreach/top.v
...@@ -16,9 +16,15 @@ module top(clk, rst, a, b, c, x, y, z); ...@@ -16,9 +16,15 @@ module top(clk, rst, a, b, c, x, y, z);
end else begin end else begin
case (state) case (state)
1: begin 1: begin
`ifndef BUG
x <= x; x <= x;
y <= b; y <= b;
z <= 1; z <= 1;
`else
x <= 5'd0;
y <= 5'd0;
z <= 5'd0;
`endif
end end
2: begin 2: begin
x <= a; x <= a;
......
simple/inout_port/testbench.v
...@@ -15,40 +15,26 @@ module testbench; ...@@ -15,40 +15,26 @@ module testbench;
end end
reg dinA; reg dinA = 0;
wire [1:0] dinB; wire [1:0] dioB;
wire [1:0] dinC; wire [1:0] doutC;
top uut ( top uut (
.en (en ), .en (en ),
.a (dinA ), .a (dinA ),
.b (dinB ), .b (dioB ),
.c (dinC ) .c (doutC )
); );
initial begin always @(posedge en) begin
dinA <= 0; #3;
dinA <= !dinA;
repeat (20000) #3 dinA = !dinA; end
end
assert b_test(.en(en), .A(dinA), .B(dinB[0])); assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
assert c_test(.en(en), .A(dinA), .B(dinC[0])); assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
assert cz_test(.en(!en), .A(1'bZ), .B(dinC[0])); assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
endmodule endmodule
module assert(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A != B)
begin
$display("ASSERTION FAILED in %m:",$time," ",A," ",B);
//$finish;
end
end
endmodule
simple/inout_port/top.v
...@@ -3,14 +3,20 @@ module tristate (en, i, io, o); ...@@ -3,14 +3,20 @@ module tristate (en, i, io, o);
input i; input i;
inout [1:0] io; inout [1:0] io;
output [1:0] o; output [1:0] o;
`ifndef BUG
always @(en or i) assign io[0] = (en)? i : 1'bZ;
io[0] <= (en)? i : 1'bZ;
always @(en or i) assign io[1] = (i)? en : 1'bZ;
io[1] <= (i)? en : 1'bZ;
assign o = io; assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
endmodule endmodule
......
simple/inout_port_demote/testbench.v
...@@ -15,41 +15,27 @@ module testbench; ...@@ -15,41 +15,27 @@ module testbench;
end end
reg dinA; reg dinA = 0;
wire [1:0] dinB; wire [1:0] dioB;
wire [1:0] dinC; wire [1:0] doutC;
top uut ( top uut (
.en (en ), .en (en ),
.a (dinA ), .a (dinA ),
.b (dinB ), .b (dioB ),
.c (dinC ) .c (doutC )
); );
initial begin always @(posedge en) begin
dinA <= 0; #3;
dinA <= !dinA;
repeat (20000) #3 dinA = !dinA; end
end
assert b_test(.en(en), .A(dinA), .B(dinB[0])); assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
assert c_test(.en(en), .A(dinA), .B(dinC[0])); assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
assert cz_test(.en(!en), .A(1'bZ), .B(dinC[0])); assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
endmodule endmodule
module assert(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A != B)
begin
$display("ASSERTION FAILED in %m:",$time," ",A," ",B);
//$finish;
end
end
endmodule
simple/inout_port_demote/top.v
...@@ -3,7 +3,7 @@ module tristate (en, i, io, o); ...@@ -3,7 +3,7 @@ module tristate (en, i, io, o);
input i; input i;
inout [1:0] io; inout [1:0] io;
output [1:0] o; output [1:0] o;
`ifndef BUG
always @(en or i) always @(en or i)
io[0] <= (en)? i : 1'bZ; io[0] <= (en)? i : 1'bZ;
...@@ -11,6 +11,15 @@ module tristate (en, i, io, o); ...@@ -11,6 +11,15 @@ module tristate (en, i, io, o);
io[1] <= (i)? en : 1'bZ; io[1] <= (i)? en : 1'bZ;
assign o = (en)? io : 2'bZZ; assign o = (en)? io : 2'bZZ;
`else
always @(en or i)
io[0] <= (en)? ~i : 1'bZ;
always @(en or i)
io[1] <= (i)? ~en : 1'bZ;
assign o = (en)? ~io : 2'bZZ;
`endif
endmodule endmodule
......
simple/macc/testbench.v
...@@ -21,7 +21,7 @@ module testbench; ...@@ -21,7 +21,7 @@ module testbench;
reg rst; reg rst;
wire [47:0] p; wire [47:0] p;
top uut ( top uut_macc (
.p (p), .p (p),
.a (dinA), .a (dinA),
.b (dinB), .b (dinB),
...@@ -35,42 +35,47 @@ module testbench; ...@@ -35,42 +35,47 @@ module testbench;
#5 #5
rst <= 1; rst <= 1;
#5 #5
@(posedge clk);
dinA <= 38; dinA <= 38;
dinB <= 22; dinB <= 22;
carryin <= 1; carryin <= 1;
#50
repeat (10) @(posedge clk);
dinA <= 0; dinA <= 0;
dinB <= 0; dinB <= 0;
carryin <= 0; carryin <= 0;
#50
repeat (10) @(posedge clk);
dinA <= 33; dinA <= 33;
dinB <= 12; dinB <= 12;
carryin <= 0; carryin <= 0;
#50
repeat (10) @(posedge clk);
dinA <= 0; dinA <= 0;
dinB <= 0; dinB <= 0;
carryin <= 0; carryin <= 0;
end end
assert macc_test(.clk(clk), .A(dinA), .B(dinB), .C(carryin), .P(p)); uut_macc_checker macc_check(.clk(clk), .A(dinA), .B(dinB), .C(carryin), .P(p));
endmodule endmodule
module assert(input clk, input [24:0] A, input [17:0] B, input C, input [47:0] P); module uut_macc_checker(input clk, input [24:0] A, input [17:0] B, input C, input [47:0] P);
reg [47:0] p; reg [47:0] p;
always @(posedge clk) always @(posedge clk)
begin begin
//#1; #20
@(posedge clk); p <= (A * B) + C;
@(posedge clk);
@(posedge clk);
@(posedge clk);
assign p = (A * B) + C;
if (P != p) if (P != p)
begin begin
$display("ASSERTION FAILED in %m:",$time," ",P," ",p); $display("ERROR: ASSERTION FAILED in %m:",$time," ",P," ",p);
//$finish; //$stop;
end end
end end
endmodule endmodule
simple/macc/top.v
...@@ -22,7 +22,11 @@ module MACC (P, A, B, CARRYIN, CLK, RST); ...@@ -22,7 +22,11 @@ module MACC (P, A, B, CARRYIN, CLK, RST);
if(!RST) if(!RST)
P <= 'b0; P <= 'b0;
else else
`ifndef BUG
P <= mult_reg + CARRYIN; P <= mult_reg + CARRYIN;
`else
P <= mult_reg - CARRYIN;
`endif
end end
endmodule endmodule
......
simple/run.sh
...@@ -9,7 +9,7 @@ mkdir $1/work_$2 ...@@ -9,7 +9,7 @@ mkdir $1/work_$2
cd $1/work_$2 cd $1/work_$2
yosys -ql yosys.log ../../scripts/$2.ys yosys -ql yosys.log ../../scripts/$2.ys
iverilog -o testbench ../testbench.v synth.v ../../../../../techlibs/common/simcells.v iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v
if ! vvp -N testbench > testbench.log 2>&1; then if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log grep 'ERROR' testbench.log
......
simple/tristate/testbench.v
...@@ -15,34 +15,20 @@ module testbench; ...@@ -15,34 +15,20 @@ module testbench;
end end
reg dinA; reg dinA = 0;
wire dinB; wire doutB;
top uut ( top uut (
.en (en ), .en (en ),
.a (dinA ), .a (dinA ),
.b (dinB ) .b (doutB )
); );
initial begin always @(posedge en) begin
dinA <= 0; #3;
dinA <= !dinA;
repeat (20000) #3 dinA = !dinA; end
end
assert b_test(.en(en), .A(dinA), .B(dinB)); assert_tri b_test(.en(en), .A(dinA), .B(doutB));
endmodule endmodule
module assert(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A != B)
begin
$display("ASSERTION FAILED in %m:",$time," ",A," ",B);
//$finish;
end
end
endmodule
simple/tristate/top.v
...@@ -2,9 +2,15 @@ module tristate (en, i, o); ...@@ -2,9 +2,15 @@ module tristate (en, i, o);
input en; input en;
input i; input i;
output o; output o;
`ifndef BUG
always @(en or i) always @(en or i)
o <= (en)? i : 1'bZ; o <= (en)? i : 1'bZ;
`else
always @(en or i)
o <= (en)? ~i : 1'bZ;
`endif
endmodule endmodule
......
simple/tristate_case/testbench.v
...@@ -15,34 +15,20 @@ module testbench; ...@@ -15,34 +15,20 @@ module testbench;
end end
reg dinA; reg dinA = 0;
wire dinB; wire doutB;
top uut ( top uut (
.en (en ), .en (en ),
.a (dinA ), .a (dinA ),
.b (dinB ) .b (doutB )
); );
initial begin always @(posedge en) begin
dinA <= 0; #3;
dinA <= !dinA;
repeat (20000) #3 dinA = !dinA; end
end
assert b_test(.en(en), .A(dinA), .B(dinB)); assert_tri b_test(.en(en), .A(dinA), .B(doutB));
endmodule endmodule
module assert(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A != B)
begin
$display("ASSERTION FAILED in %m:",$time," ",A," ",B);
//$finish;
end
end
endmodule
simple/tristate_case/top.v
...@@ -6,7 +6,11 @@ module tristate (en, i, o); ...@@ -6,7 +6,11 @@ module tristate (en, i, o);
always @(en or i) always @(en or i)
begin begin
case (en) case (en)
`ifndef BUG
1:o <= i; 1:o <= i;
`else
1:o <= ~i;
`endif
default :o <= 1'bZ; default :o <= 1'bZ;
endcase endcase
end end
......
simple/tristate_const_0/testbench.v
...@@ -15,34 +15,20 @@ module testbench; ...@@ -15,34 +15,20 @@ module testbench;
end end
reg dinA; reg dinA = 0;
wire dinB; wire doutB;
top uut ( top uut (
.en (en ), .en (en ),
.a (dinA ), .a (dinA ),
.b (dinB ) .b (doutB )
); );
initial begin always @(posedge en) begin
dinA <= 0; #3;
dinA <= !dinA;
repeat (20000) #3 dinA = !dinA; end
end
assert b_test(.en(en), .A(dinA), .B(dinB)); assert_tri b_test(.en(en), .A(1'bZ), .B(doutB));
endmodule endmodule
module assert(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A === B)
begin
$display("ASSERTION FAILED in %m:",$time," ",A," ",B);
//$finish;
end
end
endmodule
simple/tristate_const_0/top.v
...@@ -4,7 +4,11 @@ module tristate (en, i, o); ...@@ -4,7 +4,11 @@ module tristate (en, i, o);
output o; output o;
always @(en or i) always @(en or i)
`ifndef BUG
o <= (en)? i : 1'bZ; o <= (en)? i : 1'bZ;
`else
o <= (en)? ~i : 1'bZ;
`endif
endmodule endmodule
......
simple/tristate_const_1/testbench.v
...@@ -15,34 +15,20 @@ module testbench; ...@@ -15,34 +15,20 @@ module testbench;
end end
reg dinA; reg dinA = 0;
wire dinB; wire doutB;
top uut ( top uut (
.en (en ), .en (en ),
.a (dinA ), .a (dinA ),
.b (dinB ) .b (doutB )
); );
initial begin always @(posedge en) begin
dinA <= 0; #3;
dinA <= !dinA;
repeat (20000) #3 dinA = !dinA; end
end
assert b_test(.en(en), .A(dinA), .B(dinB)); assert_tri b_test(.en(en), .A(dinA), .B(doutB));
endmodule endmodule
module assert(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A !== B)
begin
$display("ASSERTION FAILED in %m:",$time," ",A," ",B);
//$finish;
end
end
endmodule
simple/tristate_const_1/top.v
...@@ -4,7 +4,11 @@ module tristate (en, i, o); ...@@ -4,7 +4,11 @@ module tristate (en, i, o);
output o; output o;
always @(en or i) always @(en or i)
`ifndef BUG
o <= (en)? i : 1'bZ; o <= (en)? i : 1'bZ;
`else
o <= (en)? ~i : 1'bZ;
`endif
endmodule endmodule
......
simple/tristate_const_data/testbench.v
...@@ -15,34 +15,20 @@ module testbench; ...@@ -15,34 +15,20 @@ module testbench;
end end
reg dinA; reg dinA = 0;
wire dinB; wire doutB;
top uut ( top uut (
.en (en ), .en (en ),
.a (dinA ), .a (dinA ),
.b (dinB ) .b (doutB )
); );
initial begin always @(posedge en) begin
dinA <= 0; #3;
dinA <= !dinA;
repeat (20000) #3 dinA = !dinA; end
end
assert b_test(.en(en), .A(dinA), .B(dinB)); assert_tri b_test(.en(en), .A(1'b0), .B(doutB));
endmodule endmodule
module assert(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A != B)
begin
$display("ASSERTION FAILED in %m:",$time," ",A," ",B);
//$finish;
end
end
endmodule
simple/tristate_const_data/top.v
...@@ -16,7 +16,11 @@ output b ...@@ -16,7 +16,11 @@ output b
tristate u_tri ( tristate u_tri (
.en (en ), .en (en ),
.i (1'bZ ), `ifndef BUG
.i (1'b0 ),
`else
.i (a ),
`endif
.o (b ) .o (b )
); );
......
simple/tristate_if/testbench.v
...@@ -15,34 +15,20 @@ module testbench; ...@@ -15,34 +15,20 @@ module testbench;
end end
reg dinA; reg dinA = 0;
wire dinB; wire doutB;
top uut ( top uut (
.en (en ), .en (en ),
.a (dinA ), .a (dinA ),
.b (dinB ) .b (doutB )
); );
initial begin always @(posedge en) begin
dinA <= 0; #3;
dinA <= !dinA;
repeat (20000) #3 dinA = !dinA; end
end
assert b_test(.en(en), .A(dinA), .B(dinB)); assert_tri b_test(.en(en), .A(dinA), .B(doutB));
endmodule endmodule
module assert(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A != B)
begin
$display("ASSERTION FAILED in %m:",$time," ",A," ",B);
//$finish;
end
end
endmodule
simple/tristate_if/top.v
...@@ -6,7 +6,11 @@ module tribuf (en, i, o); ...@@ -6,7 +6,11 @@ module tribuf (en, i, o);
always @* always @*
begin begin
if (en) if (en)
`ifndef BUG
o = i; o = i;
`else
o = ~i;
`endif
else else
o = 1'bZ; o = 1'bZ;
end end
......
simple/tristate_proc_asmt/testbench.v
...@@ -15,34 +15,20 @@ module testbench; ...@@ -15,34 +15,20 @@ module testbench;
end end
reg dinA; reg dinA = 0;
wire dinB; wire doutB;
top uut ( top uut (
.en (en ), .en (en ),
.a (dinA ), .a (dinA ),
.b (dinB ) .b (doutB )
); );
initial begin always @(posedge en) begin
dinA <= 0; #3;
dinA <= !dinA;
repeat (20000) #3 dinA = !dinA; end
end
assert b_test(.en(en), .A(dinA), .B(dinB)); assert_tri b_test(.en(en), .A(dinA), .B(doutB));
endmodule endmodule
module assert(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A != B)
begin
$display("ASSERTION FAILED in %m:",$time," ",A," ",B);
//$finish;
end
end
endmodule
simple/tristate_proc_asmt/top.v
...@@ -3,7 +3,11 @@ module tristate (en, i, o); ...@@ -3,7 +3,11 @@ module tristate (en, i, o);
input i; input i;
output o; output o;
`ifndef BUG
assign o = (en)? i : 1'bZ; assign o = (en)? i : 1'bZ;
`else
assign o = (en)? ~i : 1'bZ;
`endif
endmodule endmodule
......
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