verific/vhdl/test.ys · abd361f826101363aba377c7c2353e6bfbfc9d5d · lvzhengyang / yosys-tests · GitLab

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Add simple verific VHDL test case · 42963512
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Clifford Wolf committed Aug 22, 2018
42963512

test.ys 205 Bytes