verific/vhdl/tb.sv · 184c3c3ef8dd447ea6558a86ca7d5ff03ebf7dbb · lvzhengyang / yosys-tests · GitLab

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Add simple verific VHDL test case · 42963512
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Clifford Wolf committed Aug 22, 2018
42963512

tb.sv 250 Bytes