Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
Y
yosys-tests
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
yosys-tests
Repository
10d552218bfc176a1ae3cd346ae3d9f878bbe9ca
Switch branch/tag
yosys-tests
architecture
xilinx_ug901_synthesis_examples
ram_simple_dual_one_clock.v
Find file
Blame
History
Permalink
Move tests for Xilinx UG901 examples from tests/xilinx_ug901 to yosys-tests
· 2d5dab20
SergeyDegtyar
committed
Sep 10, 2019
2d5dab20
ram_simple_dual_one_clock.v
475 Bytes
Edit
