Blame · architecture/scripts/synth_ice40_min_ce.ys · f23b8ba1538808d007e01f5968fcc8b38c131f3c · lvzhengyang / yosys-tests · GitLab

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synth_ice40_min_ce.ys 75 Bytes

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Add new tests to backends and architecture;

committed 5 years ago

read_verilog ../top.v
synth_ice40 -dffe_min_ce_use 2
write_verilog synth.v