Blame · backends/scripts/write_ilang_selected.ys · e772f54beb4b127c8fc0ec66f770d5e5b6538824 · lvzhengyang / yosys-tests · GitLab

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Add tests for "II architecture" and "III backends"; fix testbench for simple/memory; f7c7f7c7 SergeyDegtyar committed 6 years ago	1	`read_verilog ../top.v`
Add new tests to backends and architecture; 10f53cb1 SergeyDegtyar committed 5 years ago	2	`write_ilang -selected ilang.ilang`
Add tests for "II architecture" and "III backends"; fix testbench for simple/memory; f7c7f7c7 SergeyDegtyar committed 6 years ago	3 4 5 6	`proc dump -a file.il write_ilang -selected ilang.ilang dump -m -a file1.il`
Add new tests to backends and architecture; 10f53cb1 SergeyDegtyar committed 5 years ago	7	`write_verilog synth.v`