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lvzhengyang
yosys-tests
d5339b419cdc643c07c97c30bec487cdbc7bf50e
d5339b419cdc643c07c97c30bec487cdbc7bf50e
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yosys-tests
architecture
scripts
synth_intel_invalid_family.ys
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synth_intel_invalid_family.ys
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Add tests for error mesages for 'architecture' test group.
27aa4af7
SergeyDegtyar
committed
5 years ago
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read_verilog ../top.v
synth_intel -family u
write_verilog synth.v
