Blame · backends/scripts/write_aiger_map.ys · c7aecef2f993051787327de98f8066468cc5d8bf · lvzhengyang / yosys-tests · GitLab

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Add tests for "II architecture" and "III backends"; fix testbench for simple/memory; f7c7f7c7 SergeyDegtyar committed 6 years ago	1 2 3	`read_verilog -sv ../top.v aigmap write_aiger -map a.map aiger.aiger`
Fix failed tests 5fee7bf3 SergeyDegtyar committed 5 years ago	4 5 6 7	`design -reset read_verilog -sv ../top_clean.v aigmap write_aiger aiger.aiger`
Add tests for "II architecture" and "III backends"; fix testbench for simple/memory; f7c7f7c7 SergeyDegtyar committed 6 years ago	8 9	`synth -top top write_verilog synth.v`