read_verilog ../top.v prep -flatten -top top splitnets -ports;; design -stash gold read_verilog ../synth_top.v read_verilog ../logic.v prep -flatten -top top splitnets -ports;; design -stash gate design -copy-from gold -as gold top design -copy-from gate -as gate top equiv_make gold gate equiv design -save something design -push equiv_add golddd gate design -reset read_verilog ../top.v write_verilog synth.v
