Blame · simple/scripts/clk2fflogic_mem.ys · bb79f23b9ebf569d04b2388a91bf6fa6c92cc04f · lvzhengyang / yosys-tests · GitLab

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Commit tests for "I Simple" tasks section fae17050 SergeyDegtyar committed 6 years ago	1 2 3 4	`read_verilog ../top.v memory_collect proc clk2fflogic`
Add checks for certain cell type into 'simple' tests. 9ab6e149 SergeyDegtyar committed 5 years ago	5	`tee -o result.log dump`
Commit tests for "I Simple" tasks section fae17050 SergeyDegtyar committed 6 years ago	6 7 8 9	`synth -top top design -reset read_verilog ../top.v synth -top top`
Add checks for certain cell type into 'simple' tests. 9ab6e149 SergeyDegtyar committed 5 years ago	10	`write_verilog synth.v`