Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
Y
yosys-tests
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
yosys-tests
971f48272cc8d9da3a59cf8f74aa17d6cd03931d
971f48272cc8d9da3a59cf8f74aa17d6cd03931d
Switch branch/tag
yosys-tests
architecture
scripts
synth_intel_max10.ys
Find file
Normal view
History
Permalink
synth_intel_max10.ys
71 Bytes
Edit
Newer
Older
Add tests for "II architecture" and "III backends"; fix testbench for simple/memory;
f7c7f7c7
SergeyDegtyar
committed
6 years ago
1
2
3
read_verilog ../top.v
synth_intel -family max10
write_verilog synth.v
