Blame · backends/scripts/write_verilog_lut.ys · 91d39446f496508be7f9653a92c18bbdc0d1b9e3 · lvzhengyang / yosys-tests · GitLab

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write_verilog_lut.ys 66 Bytes

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Add new tests to 'backends'

committed 5 years ago

read_verilog ../top.v
proc
synth
abc -lut 5
write_verilog synth.v