Blame · simple/scripts/full_adder.ys · 753930e762ea8b7d219f4b9267b442303e68907f · lvzhengyang / yosys-tests · GitLab

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Commit tests for "I Simple" tasks section

committed 6 years ago

read_verilog ../top.v
synth -top top
extract_fa -fa -v
synth -top top
write_verilog synth.v