read_verilog ../top.v proc fsm_detect fsm_extract fsm_recode -encfile encfile.fsm design -stash gold read_verilog ../synth_top.v read_verilog ../logic.v proc design -stash gate design -copy-from gold -as gold top design -copy-from gate -as gate top equiv_make -encfile encfile.fsm gold gate equiv design -reset read_verilog ../top.v proc write_verilog synth.v
