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lvzhengyang
yosys-tests
5b39f7c6c241ec3f15f1fb5921fd8b478d75aa72
5b39f7c6c241ec3f15f1fb5921fd8b478d75aa72
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yosys-tests
architecture
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synth_sf2_edif.ys
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synth_sf2_edif.ys
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Add tests for "II architecture" and "III backends"; fix testbench for simple/memory;
f7c7f7c7
SergeyDegtyar
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6 years ago
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read_verilog ../top.v
synth_sf2 -edif edif.edif
write_verilog synth.v
