Blame · architecture/scripts/synth_intel_fully_selected.ys · 45c0ea8c55e0184c68b0045bd8683e25110cbee8 · lvzhengyang / yosys-tests · GitLab

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Add tests for error mesages for 'architecture' test group.

committed 5 years ago

read_verilog ../top.v
select dffe
synth_intel
write_verilog synth.v