read_verilog ../bytewrite_tdp_ram_readfirst2.v hierarchy -top bytewrite_tdp_ram_readfirst2 proc memory -nomap equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx memory opt -full # TODO #equiv_opt -run prove: -assert null miter -equiv -flatten -make_assert -make_outputs gold gate miter #sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter design -load postopt cd bytewrite_tdp_ram_readfirst2 stat #Vivado synthesizes 1 RAMB36E1. select -assert-count 1 t:$mem select -assert-count 8 t:LUT2 select -assert-count 64 t:LUT3 select -assert-none t:LUT2 t:LUT3 t:$mem %% t:* %D
