Blame · simple/scripts/hierarchy_keep_portwidths.ys · 3d49abc1a9514500d772280dac55dc0c244d3ca9 · lvzhengyang / yosys-tests · GitLab

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hierarchy_keep_portwidths.ys 96 Bytes

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Commit tests for "I Simple" tasks section

committed 6 years ago

read_verilog ../top.v
hierarchy -keep_portwidths -top top
synth -top top
write_verilog synth.v