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write_aiger_symbols.ys 181 Bytes
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Add tests for "II architecture" and "III backends"; fix testbench for simple/memory;
f7c7f7c7
 
SergeyDegtyar committed
1 2 3 
read_verilog -sv ../top.v
aigmap
write_aiger -symbols aiger.aiger
Fix failed tests
5fee7bf3
 
SergeyDegtyar committed
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design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
Add tests for "II architecture" and "III backends"; fix testbench for simple/memory;
f7c7f7c7
 
SergeyDegtyar committed
8 9 
synth -top top
write_verilog synth.v